公开(公告)号：US20180006491A1

公开(公告)日：2018-01-04

申请号：US15702354

申请日：2017-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoki YASUKAWA ,  Akira OIZUMI ,  Toyohiko YOSHIDA ,  Yoshinori TOKIOKA

IPC: H02J9/06 ,  H02J1/10

CPC classification number: H02J9/061 ,  H02J1/10

Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.

公开(公告)号：US20150097601A1

公开(公告)日：2015-04-09

申请号：US14571211

申请日：2014-12-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeki NAKAMURA ,  Shintaro MORI ,  Yoshinori TOKIOKA ,  Kenji TOKAMI

IPC: H03K17/22 ,  H03K3/012

CPC classification number: H03K17/223 ,  H03K3/012 ,  H03L5/02

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract translation: 提供一种设置有可以可靠地检测电源电压降低的上电复位电路的半导体器件。 设置在半导体器件上的上电复位电路包括：将初级电压与参考值进行比较的第一比较电路; 以及将次级电压与参考值进行比较的第二比较电路。 基于第一和第二比较电路的比较结果，上电复位电路发出复位信号。

公开(公告)号：US20180196500A1

公开(公告)日：2018-07-12

申请号：US15915788

申请日：2018-03-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori TOKIOKA ,  Soichi KOBAYASHI ,  Akira OIZUMI

IPC: G06F1/32 ,  G06F1/24

CPC classification number: G06F1/3296 ,  G06F1/24 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  H03K17/223 ,  H03L5/00 ,  Y02D10/172 ,  Y02D50/20

Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

公开(公告)号：US20160065001A1

公开(公告)日：2016-03-03

申请号：US14843823

申请日：2015-09-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoki YASUKAWA ,  Akira OIZUMI ,  Toyohiko YOSHIDA ,  Yoshinori TOKIOKA

IPC: H02J9/06

CPC classification number: H02J9/061 ,  H02J1/10

Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.

Abstract translation: 所公开的发明旨在防止内部电路的故障，因为在由备用电源供电的半导体器件的操作期间由噪声引起的不期望的电源切换，同时消除备用电源的浪费的消耗。 在将备用电源端子连接到内部电源节点之后，将备用电源端子与内部电源节点解耦之前，将主电源端子耦合到内部电源节点之后的第一切换转换时间比第二切换时间长 电源节点，直到主电源端子与内部电源节点断开。

公开(公告)号：US20150378426A1

公开(公告)日：2015-12-31

申请号：US14845060

申请日：2015-09-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori TOKIOKA ,  Soichi KOBAYASHI ,  Akira OIZUMI

IPC: G06F1/32 ,  G06F1/24

CPC classification number: G06F1/3296 ,  G06F1/24 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  H03K17/223 ,  H03L5/00 ,  Y02D10/172 ,  Y02D50/20

Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

Abstract translation: 提供一种能够减少上电时的浪费待机时间的半导体装置。 在该半导体器件中，内部电路的复位被消除，如下所述。 当存储在存储部分中的数据信号为“0”时，当在上电复位信号的上升沿之后经过相当短的时间时，通过使内部复位信号变为“H”电平来解除复位。 当数据信号为“1”时，在上电复位信号的上升沿过去相对较长的时间后，通过将内部复位信号置“H”电平来解除复位。 因此，通过将逻辑上等同于电源电压的上升时间的数据信号写入存储部分，可以减少上电浪费的待机时间。

公开(公告)号：US20170160792A1

公开(公告)日：2017-06-08

申请号：US15439175

申请日：2017-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori TOKIOKA ,  Soichi KOBAYASHI ,  Akira OIZUMI

IPC: G06F1/32 ,  G06F1/24

CPC classification number: G06F1/3296 ,  G06F1/24 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  H03K17/223 ,  H03L5/00 ,  Y02D10/172 ,  Y02D50/20

Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

公开(公告)号：US20150155854A1

公开(公告)日：2015-06-04

申请号：US14547997

申请日：2014-11-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keiichi HAYASAKA ,  Toyohiko YOSHIDA ,  Akira OIZUMI ,  Yoshinori TOKIOKA

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K19/0008 ,  G06F1/24 ,  G06F1/30

Abstract: There is a need to provide a technology that shortens a time period from a point to start an external power supply for a microcontroller to a point to start operating a logic circuit. A stable voltage supply circuit of a semiconductor circuit accepts an external power supply VCC and supplies a VDD line with one of a power supply voltage to cause a stable output voltage and a power supply voltage to cause an unstable output voltage and fast start. At startup, the semiconductor circuit accepts an external power supply. The semiconductor circuit raises a power supply voltage to cause a stable output voltage and supplies a logic portion initialization circuit with an unstable power supply voltage to fast start, and initializes a VDD operation circuit. When the output voltage is stabilized, the semiconductor circuit changes a power supply voltage supplied to the VDD line and starts operating the VDD operation circuit.

Abstract translation: 需要提供一种技术，其缩短从微控制器的外部电源点开始运行逻辑电路的时间点。 半导体电路的稳定电压供给电路接受外部电源VCC，并且向VDD线提供电源电压中的一个，以产生稳定的输出电压和电源电压，从而导致不稳定的输出电压并快速启动。 在启动时，半导体电路接受外部电源。 半导体电路提高电源电压以产生稳定的输出电压，并向具有不稳定电源电压的逻辑部分初始化电路提供快速启动，并初始化VDD操作电路。 当输出电压稳定时，半导体电路改变提供给VDD线的电源电压，并开始运行VDD运行电路。

公开(公告)号：US20140084972A1

公开(公告)日：2014-03-27

申请号：US14036763

申请日：2013-09-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeki NAKAMURA ,  Shintaro MORI ,  Yoshinori TOKIOKA ,  Kenji TOKAMI

IPC: H03L5/02

CPC classification number: H03K17/223 ,  H03K3/012 ,  H03L5/02

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract translation: 提供一种设置有可以可靠地检测电源电压降低的上电复位电路的半导体器件。 设置在半导体器件上的上电复位电路包括：将初级电压与参考值进行比较的第一比较电路; 以及将次级电压与参考值进行比较的第二比较电路。 基于第一和第二比较电路的比较结果，上电复位电路发出复位信号。