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公开(公告)号：US20150378351A1
公开(公告)日：2015-12-31
申请号：US14843654
申请日：2015-09-02
Applicant: Renesas Electronics Corporation
Inventor： Takehiro SHIMIZU , Toshio Asai
IPC: G05B19/408 , H02N2/14 , H02N2/16 , H03K7/08 , G05B15/02
CPC classification number: G05B19/408 , G05B15/02 , G05B2219/37479 , G06F9/30007 , G06F9/3001 , H02N2/14 , H02N2/16 , H03K5/15013 , H03K7/08
Abstract: An apparatus including an ultrasonic motor having an electrostrictive element of a stator for driving a rotor thereof; and a microcontroller having a central processing unit (CPU), a built-in memory (ROM) and a pulse generating circuit which generates an pulse output signal which is applied to the electrostrictive element of the ultrasonic motor, wherein the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register, a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator, wherein the counter starts to count up, incrementing its count value from a count initial value, wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it.
Abstract translation: 一种包括具有用于驱动其转子的定子的电致伸缩元件的超声波马达的装置; 以及具有中央处理单元（CPU），内置存储器（ROM）和产生施加到超声波马达的电致伸缩元件的脉冲输出信号的脉冲发生电路的微控制器，其中，脉冲发生电路包括： 上升设置寄存器，下降设置寄存器，相位调整数据寄存器，周期数据寄存器，相位运算电路，计数器，第一比较器，第二比较器和脉冲发生器，其中计数器开始计数，递增 其计数初始值的计数值，其中循环数据寄存器将计数器的计数最大值作为周期数据存储到计数器。
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公开(公告)号：US09170577B2
公开(公告)日：2015-10-27
申请号：US13888258
申请日：2013-05-06
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu , Toshio Asai
CPC classification number: G05B19/408 , G05B15/02 , G05B2219/37479 , G06F9/30007 , G06F9/3001 , H02N2/14 , H02N2/16 , H03K5/15013 , H03K7/08
Abstract: It is intended to reduce the amount of computation to be performed by CPU or the required amount of storage space in a built-in memory for timing adjustment of a pulse output signal. A digital multiplying circuit in the phase arithmetic circuit of the pulse generating circuit generates a multiplication output signal by multiplying a phase angle change value in the phase adjustment data register and a count maximum value Nmax in the cycle data register. A digital dividing circuit generates a division output signal by dividing the multiplication output signal by 360 degrees of phase angle for one cycle. A digital adding circuit adds the division output signal and rise setting/fall setting count values and a subtracting circuit subtracts the division output signal from these values. The addition and subtraction generate new rise setting/fall setting count values required to delay/advance the phase by the phase angle change value.
Abstract translation: 旨在减少由CPU执行的计算量或内置存储器中所需的存储空间量，用于脉冲输出信号的定时调整。 脉冲发生电路的相位运算电路中的数字乘法电路通过将相位调整数据寄存器中的相位角变化值与周期数据寄存器中的计数最大值Nmax相乘来生成乘法输出信号。 数字分频电路通过将乘法输出信号除以360度的相位角来生成一个分频输出信号，以进行一个周期。 数字加法电路将除法输出信号和上升设定/下降设定计数值相加，减法电路从这些值中减去除法输出信号。 加和减产生相位角变化值延迟/提前所需的新的上升设定/下降设定计数值。
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公开(公告)号：US09904275B2
公开(公告)日：2018-02-27
申请号：US14843654
申请日：2015-09-02
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu , Toshio Asai
CPC classification number: G05B19/408 , G05B15/02 , G05B2219/37479 , G06F9/30007 , G06F9/3001 , H02N2/14 , H02N2/16 , H03K5/15013 , H03K7/08
Abstract: An apparatus including an ultrasonic motor having an electrostrictive element of a stator for driving a rotor thereof; and a microcontroller having a central processing unit (CPU), a built-in memory (ROM) and a pulse generating circuit which generates an pulse output signal which is applied to the electrostrictive element of the ultrasonic motor, wherein the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register, a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator, wherein the counter starts to count up, incrementing its count value from a count initial value, wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it.
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