-
公开(公告)号：US09608654B2
公开(公告)日：2017-03-28
申请号：US15078944
申请日：2016-03-23
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu
Abstract: The present invention provides a semiconductor device having a high-speed A/D conversion circuit realizing improvement in noise resistance. A semiconductor device having an A/D conversion circuit includes a sample and hold circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period, and prediction tables. The prediction tables have reference voltage information designating a reference voltage to be compared with an analog signal output from the sample and hold circuit at a plurality of timings in the first period and bit position information designating a bit position of a digital signal determined by comparison with the reference voltage.
-
Patent Agency Ranking
公开(公告)号：US09904275B2
公开(公告)日：2018-02-27
申请号：US14843654
申请日：2015-09-02
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu , Toshio Asai
CPC classification number: G05B19/408 , G05B15/02 , G05B2219/37479 , G06F9/30007 , G06F9/3001 , H02N2/14 , H02N2/16 , H03K5/15013 , H03K7/08
Abstract: An apparatus including an ultrasonic motor having an electrostrictive element of a stator for driving a rotor thereof; and a microcontroller having a central processing unit (CPU), a built-in memory (ROM) and a pulse generating circuit which generates an pulse output signal which is applied to the electrostrictive element of the ultrasonic motor, wherein the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register, a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator, wherein the counter starts to count up, incrementing its count value from a count initial value, wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it.
-
3.发明授权公开(公告)号：US12136931B2
公开(公告)日：2024-11-05
申请号：US17983576
申请日：2022-11-09
Applicant: Renesas Electronics Corporation
Inventor： Pratama Fajarmega , Tatsuo Nishino , Takehiro Shimizu
Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.
-
公开(公告)号：US11086386B2
公开(公告)日：2021-08-10
申请号：US16059924
申请日：2018-08-09
Applicant: Renesas Electronics Corporation
Inventor： Shunsuke Kogure , Takehiro Shimizu , Tatsuwo Nishino
IPC: G06F1/3234 , G06F1/3296 , G06F1/3203 , H02P23/00 , H02P27/00
Abstract: The power consumption of a circuit block outside a microcomputer and inside the same system is reduced. An electric power control system includes a first power supply circuit, a semiconductor device having a first circuit block operated by electric power supplied from the first power supply circuit, a state holding circuit that holds an operation state in the first circuit block according to the electric power, an electric power control circuit that controls the electric power supplied to the first circuit block according to the operation state, and a first terminal that outputs a first state signal corresponding to the operation state, a second power supply circuit that controls the supply of electric power according to the first state signal, and a second circuit block operated by the electric power supplied from the second power supply circuit.
-
公开(公告)号：US09998132B2
公开(公告)日：2018-06-12
申请号：US15435001
申请日：2017-02-16
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu
Abstract: A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.
-
公开(公告)号：US09170577B2
公开(公告)日：2015-10-27
申请号：US13888258
申请日：2013-05-06
Applicant: Renesas Electronics Corporation
Inventor： Takehiro Shimizu , Toshio Asai
CPC classification number: G05B19/408 , G05B15/02 , G05B2219/37479 , G06F9/30007 , G06F9/3001 , H02N2/14 , H02N2/16 , H03K5/15013 , H03K7/08
Abstract: It is intended to reduce the amount of computation to be performed by CPU or the required amount of storage space in a built-in memory for timing adjustment of a pulse output signal. A digital multiplying circuit in the phase arithmetic circuit of the pulse generating circuit generates a multiplication output signal by multiplying a phase angle change value in the phase adjustment data register and a count maximum value Nmax in the cycle data register. A digital dividing circuit generates a division output signal by dividing the multiplication output signal by 360 degrees of phase angle for one cycle. A digital adding circuit adds the division output signal and rise setting/fall setting count values and a subtracting circuit subtracts the division output signal from these values. The addition and subtraction generate new rise setting/fall setting count values required to delay/advance the phase by the phase angle change value.
Abstract translation: 旨在减少由CPU执行的计算量或内置存储器中所需的存储空间量，用于脉冲输出信号的定时调整。 脉冲发生电路的相位运算电路中的数字乘法电路通过将相位调整数据寄存器中的相位角变化值与周期数据寄存器中的计数最大值Nmax相乘来生成乘法输出信号。 数字分频电路通过将乘法输出信号除以360度的相位角来生成一个分频输出信号，以进行一个周期。 数字加法电路将除法输出信号和上升设定/下降设定计数值相加，减法电路从这些值中减去除法输出信号。 加和减产生相位角变化值延迟/提前所需的新的上升设定/下降设定计数值。
-
-
-
-
-
Search Results
6
records
(took 0.012 seconds)
