公开(公告)号：US20040111571A1

公开(公告)日：2004-06-10

申请号：US10454500

申请日：2003-06-05

Applicant: Renesas Technology Corp.

Inventor： Koji Nii

IPC: G06F012/00

CPC classification number: G11C15/04 ,  G11C8/10 ,  G11C11/413

Abstract: It is an object to obtain a semiconductor storage having a 1nullchip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1nullport memory cell array (11) provided with a word line (WL1) for a first port in common and a 2nullport memory cell array (12) are provided together over one chip, thereby constituting a semiconductor storage. By selectively bringing any of a plurality of the word lines (WL1) for the first port into an active state by a row decoder (16), it is possible to simultaneously access respective memory cells of the 1nullport memory cell array (11) and the 2nullport memory cell array (12). By selectively bringing any of a plurality of word lines (WL2) for a second port into an active state by a row decoder (18), it is possible to singly access the 2nullport memory cell array (12).

Abstract translation: 本发明的目的是获得具有可以同时访问存储在不同存储单元阵列中的存储单元的1芯片结构的半导体存储器。 具有用于第一共用端口的字线（WL1）和2端口存储单元阵列（12）的1端口存储单元阵列（11）一起设置在一个芯片上，由此构成半导体存储器。 通过选择性地使行解码器（16）将用于第一端口的多个字线（WL1）中的任一个作为活动状态，可以同时访问1端口存储单元阵列（11）的各个存储单元， 和2端口存储单元阵列（12）。 通过选择性地使行解码器（18）将用于第二端口的多个字线（WL2）中的任一个作为活动状态，可以单独访问2端口存储单元阵列（12）。

公开(公告)号：US20040042275A1

公开(公告)日：2004-03-04

申请号：US10445934

申请日：2003-05-28

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS DEVICE DESIGN CORP.

Inventor： Tomoaki Yoshizawa ,  Koji Nii ,  Susumu Imaoka

IPC: G11C005/00

CPC classification number: G11C29/026 ,  G11C7/06 ,  G11C7/14 ,  G11C11/41 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/065

Abstract: A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dummy circuit. A potential of this dummy bit line is detected by a dummy sense amplifier, and a sense enable signal is generated. Therefore, it is possible to accurately detect a sense timing irrespectively of array architecture.

Abstract translation: 对应于预定数量的字线提供包括多个虚设单元的虚拟电路。 当选择对应的字线中的任一个时，使用包含在该虚拟电路中的多个虚拟单元来驱动与正常位线的负载相等的虚拟位线。 该虚拟位线的电位由虚拟读出放大器检测，产生感测使能信号。 因此，无论阵列结构如何，都可以精确地检测感测时序。

公开(公告)号：US20040218455A1

公开(公告)日：2004-11-04

申请号：US10691707

申请日：2003-10-24

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Koji Nii

IPC: G11C008/00

CPC classification number: G11C5/063 ,  G11C8/16

Abstract: A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port 13a, and a plurality of second word lines WLB0-WLBn connected to a second port 13b. Each of a plurality of first word lines WLA0-WLAn and each of a plurality of second word lines WLB0-WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.

Abstract translation: 具有多端口存储器的半导体存储器件包括以列和行布置的多个存储单元MC，连接到第一端口13a的多个第一字线WLA0-WLAn和连接到第一端口13a的多个第二字线WLB0-WLBn 第二端口13b。 多个第一字线WLA0-WLAn和多个第二字线WLB0-WLBn中的每一个交替地布置在平面布局中。 因此获得了允许互连之间的耦合噪声减小而不增加存储单元面积的半导体存储器件。

公开(公告)号：US20040246805A1

公开(公告)日：2004-12-09

申请号：US10689344

申请日：2003-10-21

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Koji Nii

IPC: G11C005/00

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/413

Abstract: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

Abstract translation: 电平控制信号都设置为H电平，电源线的电位都设置为低于电源电位。 以这种方式，可以显着地减少存储单元阵列的等待和写入操作期间的栅极泄漏电流。 电平控制信号分别设置为L电平和H电平，并且仅一个电源线的电位被设置为低于电源电位。 以这种方式，可以减少在存储单元阵列的读取操作期间的功耗。

公开(公告)号：US20030231527A1

公开(公告)日：2003-12-18

申请号：US10445009

申请日：2003-05-27

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yasunobu Nakase ,  Koji Nii

IPC: G11C007/08

CPC classification number: G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Abstract translation: 虚拟单元被分成多个划分的虚拟列，并且分割的虚拟位线对应于分割的虚拟列排列。 这些分开的虚拟位线设置有虚拟读出放大器，其驱动感测控制线传输感测使能信号来激活读出放大器。 可以实现读出放大器的更快的激活定时。