公开(公告)号：US20040262678A1

公开(公告)日：2004-12-30

申请号：US10827295

申请日：2004-04-20

Applicant: Renesas Technology Corp.

Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

IPC: H01L029/74

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, pnull type semiconductor region and pnull type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the nnull type single crystal silicon layer 1B is null (nullnullcm), the CHSP is set to satisfy the following equation: CHSPnull3.80null0.148null.

Abstract translation: 实现沟槽栅型功率MISFET的击穿电压的升高而不增加制造步骤的数量。 在根据本发明的半导体器件的制造方法中，在一个杂质离子注入步骤中同时在栅极线区域中形成p +型半导体区域和p +型场限制环，以使它们进入 与其中形成有栅极引出电极的沟槽接触。 在形成时，假设设置在凹槽外侧的栅极引出电极的宽度为CHSP，并且n +型单晶硅层1B的电阻率为rho（Ω·cm），则将CHSP设定为满足以下 方程式：CHSP <= 3.80 + 0.148rho。

公开(公告)号：US20040166656A1

公开(公告)日：2004-08-26

申请号：US10785103

申请日：2004-02-25

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC: H01L021/336 ,  H01L031/062 ,  H01L031/113 ,  H01L021/3205 ,  H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。