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35 条记录 (耗时 0.026 秒)

    Detection, recovery and prevention of bogus branches
    1.
    发明授权
    Detection, recovery and prevention of bogus branches 失效
    检测，恢复和预防假枝

    公开(公告)号：US07334115B1

    公开(公告)日：2008-02-19

    申请号：US09608512

    申请日：2000-06-30

    申请人： Reynold V. D'Sa ,  Alan B. Kyker ,  Slade A. Morgan ,  Rebecca E. Hebda ,  Richard A. Weier ,  Robert F. Krick

    发明人： Reynold V. D'Sa ,  Alan B. Kyker ,  Slade A. Morgan ,  Rebecca E. Hebda ,  Richard A. Weier ,  Robert F. Krick

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3842 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/3861

    摘要： The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.

    摘要翻译： 本发明提供了一种用于检测和预防微处理器中的虚假分支预测和恢复的方法和装置。 从宏指令解码的微操作被存储在解码的微操作高速缓存中。 分支预测逻辑确定分支是否为假。 如果所采取的分支被确定为假的，则本发明使得从原始虚假分支微操作指令下降的微操作被标记并随后移动到处理器的后端退休。 此外，分支预测逻辑（分支预测逻辑存储缓冲器）被更新为分支的实际方向是什么。 以这种方式，则检测到虚假的分支，从中进一步预防和恢复。

    Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table
    2.
    发明授权
    Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table 失效
    使用指令序列号索引状态信息表从回写阶段事件信号或微分支错误预测中恢复

    公开(公告)号：US06493821B1

    公开(公告)日：2002-12-10

    申请号：US09094027

    申请日：1998-06-09

    申请人： Reynold V. D'Sa ,  Robert F. Krick ,  Rebecca E. Hebda ,  Alan B. Kyker

    发明人： Reynold V. D'Sa ,  Robert F. Krick ,  Rebecca E. Hebda ,  Alan B. Kyker

    IPC分类号： G06F938

    CPC分类号： G06F9/30174 ,  G06F9/3863

    摘要： A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.

    摘要翻译： 提供流水线微处理器。 流水线微处理器包括回写阶段，其向事件发信号并发送具有该事件的指令的序列号。 事件可能是例如故障，陷阱或分支错误预测。 流水线微处理器还包括解码级，其存储相应指令的恢复状态信息，并且响应于写回级，通过使用序列号来访问存储的信息以检索具有该事件的指令的恢复状态信息来发信号通知该事件。 恢复状态信息可以包括例如指向下一个线性指令的指针，指向分支目标指令的指针，分支预测或指令源。 事件恢复微码确定使用恢复状态信息执行的下一条指令，下一条指令在机器恢复后执行。

    System and method of maintaining and utilizing multiple return stack buffers
    3.
    发明授权
    System and method of maintaining and utilizing multiple return stack buffers 失效
    维护和利用多个返回堆栈缓冲区的系统和方法

    公开(公告)号：US06374350B1

    公开(公告)日：2002-04-16

    申请号：US09584890

    申请日：2000-06-01

    申请人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

    发明人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

    IPC分类号： G06F942

    CPC分类号： G06F9/3806 ,  G06F9/30054

    摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

    摘要翻译： 提供微处理器中的指令流水线。 指令流水线包括多个流水线单元，多个流水线单元中的每一个处理多个指令。 多个流水线单元中的至少两个是流水线的至少一些指令的源。 该流水线还包括至少两个推测返回地址堆栈，每个耦合的推测返回地址栈耦合到至少一个指令源单元。 每个推测返回地址堆栈都能够存储至少两个推测返回地址。

    Method and apparatus for performing sequential executions of elements in cooperation with a transform
    6.
    发明授权
    Method and apparatus for performing sequential executions of elements in cooperation with a transform 有权
    用于与变换协作执行元素的连续执行的方法和装置

    公开(公告)号：US06715064B1

    公开(公告)日：2004-03-30

    申请号：US09489072

    申请日：2000-01-21

    申请人： Reynold V. D'Sa ,  Slade A. Morgan ,  Alan B. Kyker ,  Gad S. Sheaffer ,  Gustavo P. Espinosa

    发明人： Reynold V. D'Sa ,  Slade A. Morgan ,  Alan B. Kyker ,  Gad S. Sheaffer ,  Gustavo P. Espinosa

    IPC分类号： G06F1500

    CPC分类号： G06F9/3848

    摘要： A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instruction. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. When the sequence of instructions subsequently passes through the pipeline again, the transform is used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

    摘要翻译： 一种基于前一分支指令的分支历史来预测分支指令的结果的方法和装置。 当指令序列通过指令执行流水线时，选择基本分支指令，为基本分支指令和后续分支指令生成历史索引，并为要预测的分支指令创建变换。 当指令序列随后再次通过流水线时，变换用于对基本分支指令的历史索引进行操作，以产生要预测的分支的历史索引。 将结果用作预测数组的索引，以访问正在预测的分支指令的预测逻辑。 通过使用预定的变换，可以在待预测的分支到达正常的预测阶段之前进行分支状态预测。