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1.发明申请公开(公告)号：US20100027171A1
公开(公告)日：2010-02-04
申请号：US12182454
申请日：2008-07-30
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
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2.发明授权公开(公告)号：US08184414B2
公开(公告)日：2012-05-22
申请号：US12182454
申请日：2008-07-30
IPC分类号： H02H9/00
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
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公开(公告)号：US08040645B2
公开(公告)日：2011-10-18
申请号：US12190158
申请日：2008-08-12
IPC分类号： H02H9/00
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
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4.发明申请公开(公告)号：US20100039740A1
公开(公告)日：2010-02-18
申请号：US12190158
申请日：2008-08-12
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
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5.发明授权Diode having a pocket implant blocked and circuits and methods employing same 有权具有口袋植入物的二极管被阻塞，电路和采用其的方法公开(公告)号：US08665570B2
公开(公告)日：2014-03-04
申请号：US13075701
申请日：2011-03-30
IPC分类号： H02H9/00
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译： 提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。 以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。 栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。 二极管包括具有阱区和其上的绝缘层的半导体衬底。 在绝缘层上形成栅电极。 阳极和阴极区域设置在阱区中。 形成P-N结。 在二极管中阻塞至少一个口袋植入物以减少电容。
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6.发明申请Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same 有权具有口袋植入物阻塞的二极管和使用相同的电路和方法公开(公告)号：US20120074496A1
公开(公告)日：2012-03-29
申请号：US13075701
申请日：2011-03-30
IPC分类号： H01L23/62 , B05C11/00 , H01L21/762 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译： 提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。 以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。 栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。 二极管包括具有阱区和其上的绝缘层的半导体衬底。 在绝缘层上形成栅电极。 阳极和阴极区域设置在阱区中。 形成P-N结。 在二极管中阻塞至少一个口袋植入物以减少电容。
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