-
公开(公告)号：US08040645B2
公开(公告)日：2011-10-18
申请号：US12190158
申请日：2008-08-12
IPC分类号： H02H9/00
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
-
2.发明申请公开(公告)号：US20100027171A1
公开(公告)日：2010-02-04
申请号：US12182454
申请日：2008-07-30
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
-
3.发明授权公开(公告)号：US08184414B2
公开(公告)日：2012-05-22
申请号：US12182454
申请日：2008-07-30
IPC分类号： H02H9/00
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
-
4.发明申请公开(公告)号：US20100039740A1
公开(公告)日：2010-02-18
申请号：US12190158
申请日：2008-08-12
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
-
5.发明授权Diode having a pocket implant blocked and circuits and methods employing same 有权具有口袋植入物的二极管被阻塞，电路和采用其的方法公开(公告)号：US08665570B2
公开(公告)日：2014-03-04
申请号：US13075701
申请日：2011-03-30
IPC分类号： H02H9/00
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译： 提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。 以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。 栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。 二极管包括具有阱区和其上的绝缘层的半导体衬底。 在绝缘层上形成栅电极。 阳极和阴极区域设置在阱区中。 形成P-N结。 在二极管中阻塞至少一个口袋植入物以减少电容。
-
6.发明申请Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same 有权具有口袋植入物阻塞的二极管和使用相同的电路和方法公开(公告)号：US20120074496A1
公开(公告)日：2012-03-29
申请号：US13075701
申请日：2011-03-30
IPC分类号： H01L23/62 , B05C11/00 , H01L21/762 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译： 提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。 以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。 栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。 二极管包括具有阱区和其上的绝缘层的半导体衬底。 在绝缘层上形成栅电极。 阳极和阴极区域设置在阱区中。 形成P-N结。 在二极管中阻塞至少一个口袋植入物以减少电容。
-
公开(公告)号：US07724485B2
公开(公告)日：2010-05-25
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译： 静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。 在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。 在一个新颖的方面，RC触发电路包括通过电阻充电的电容。 电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。 在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。 在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。 电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。
-
公开(公告)号：US20080049365A1
公开(公告)日：2008-02-28
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译： 静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。 在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。 在一个新颖的方面，RC触发电路包括通过电阻充电的电容。 电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。 在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。 在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。 电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。
-
9.发明授权Distributed building blocks of R-C clamping circuitry in semiconductor die core area 有权半导体芯片区域中R-C钳位电路的分布式构建块公开(公告)号：US08531806B2
公开(公告)日：2013-09-10
申请号：US13173977
申请日：2011-06-30
IPC分类号： H02H3/22
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译： 半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。 构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。
-
10.发明申请REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY 有权三维半导体器件接合和组装过程中降低静电放电的可能性公开(公告)号：US20130127046A1
公开(公告)日：2013-05-23
申请号：US13470692
申请日：2012-05-14
申请人： Brian M. Henderson , Ronnie A. Lindley , Dong Wook Kim , Reza Jalilizeinali , Shiqun Gu , Matthiew M. Nowak
发明人： Brian M. Henderson , Ronnie A. Lindley , Dong Wook Kim , Reza Jalilizeinali , Shiqun Gu , Matthiew M. Nowak
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L23/488 , H01L21/50 , H01L21/67092 , H01L23/60 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513
摘要： Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.
摘要翻译： 通过耦合第一半导体器件的接地平面和第二半导体器件的接地平面来组装堆叠的IC器件，以使接地平面处于基本相同的电位，从而降低静电放电敏感性。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地层产生对地的优选静电放电路径，从而减少对敏感电路元件的潜在损害。
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.018 秒)
