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1.发明申请公开(公告)号：US20100027171A1
公开(公告)日：2010-02-04
申请号：US12182454
申请日：2008-07-30
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
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2.发明授权公开(公告)号：US08184414B2
公开(公告)日：2012-05-22
申请号：US12182454
申请日：2008-07-30
IPC分类号： H02H9/00
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/50 , H01L24/02 , H01L27/0207 , H01L27/0266 , H01L2924/14 , H01L2924/3025 , H03K19/00315 , Y10T29/49117
摘要： A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.
摘要翻译： 第一I / O焊盘具有设置在第一I / O焊盘的第一端的第一型晶体管。 第二I / O焊盘具有设置在第二I / O焊盘的第一端的另一第一型晶体管。 第一I / O焊盘的第一端邻接第二I / O焊盘的第一端，因此第一型晶体管与另一第一型晶体管相邻。
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公开(公告)号：US08040645B2
公开(公告)日：2011-10-18
申请号：US12190158
申请日：2008-08-12
IPC分类号： H02H9/00
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
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4.发明申请公开(公告)号：US20100039740A1
公开(公告)日：2010-02-18
申请号：US12190158
申请日：2008-08-12
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.
摘要翻译： 在多管芯封装的一个管芯上实现的保护系统提供了用于在封装的一个或多个其它管芯上产生的过量电压的放电路径。 为封装中的某些电路提供接地路径，这些电路具有高噪声灵敏度，并且为封装中的某些电路提供了相对于高噪声敏感度电路具有低噪声灵敏度的接地路径。 多芯片的高噪声敏感电路的接地短路在一起，产生了一个共同的高噪声敏感性接地。 多芯片的低噪声敏感电路的接地短路在一起，产生一个共同的低噪声敏感性接地。 在芯片外部的封装上包含预先指定的可移除路径，这样可以使公共高噪声敏感地和公共低噪声敏感地面短路。 如果存在于短路接地上的噪声导致不可接受的性能下降，则在制造过程中可移除路径。
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公开(公告)号：US07724485B2
公开(公告)日：2010-05-25
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译： 静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。 在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。 在一个新颖的方面，RC触发电路包括通过电阻充电的电容。 电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。 在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。 在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。 电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。
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公开(公告)号：US20080049365A1
公开(公告)日：2008-02-28
申请号：US11738336
申请日：2007-04-20
申请人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
发明人： Eugene Worley , Vivek Mohan , Reza Jalilizeinali
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit uses two N-channel field effect transistors (NFETs) to conduct ESD current from a first to a second supply node. During the ESD event, an ESD detection circuit couples the gates of both NFETs to the first supply node through separate conductive paths. In one novel aspect, an RC trigger circuit includes a capacitance that is charged through a resistance. The resistance involves a P-channel transistor whose gate is coupled to the gate of the second NFET. During a normal power-up condition, the P-channel transistor is conductive, thereby preventing the RC trigger from triggering if the supply voltage VDD were to rise rapidly. In another novel aspect, a novel level-shifting inverter drives the second NFET. The level-shifting inverter uses a pull down resistor to avoid snap-back and also isolates the gate of the second NFET from a capacitively loaded third supply node.
摘要翻译： 静电放电（ESD）保护电路使用两个N沟道场效应晶体管（NFET）来传导来自第一至第二供电节点的ESD电流。 在ESD事件期间，ESD检测电路通过单独的导电路径将两个NFET的栅极耦合到第一电源节点。 在一个新颖的方面，RC触发电路包括通过电阻充电的电容。 电阻涉及其栅极耦合到第二NFET的栅极的P沟道晶体管。 在正常上电状态下，P沟道晶体管导通，如果电源电压VDD快速上升，则可防止RC触发。 在另一个新颖的方面，新颖的电平移位逆变器驱动第二NFET。 电平转换逆变器使用下拉电阻来避免卡扣，并且还将第二NFET的栅极与电容加载的第三电源节点隔离。
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公开(公告)号：US20210378651A1
公开(公告)日：2021-12-09
申请号：US17047225
申请日：2019-04-11
申请人： Vivek Mohan , Robert S. Namba
发明人： Vivek Mohan , Robert S. Namba
摘要： The present invention provides an instrument assembly that is expandable in steps for providing precise measurement of bone gap and distraction of bone in a controlled manner. It discloses a tool performing expandable Bi-Surface Mechanism to expand a bi-compartmental structure. The disclosed system is equipped with two active surfaces (Bottom base and a top plate) between which a force is applied to move the surfaces in relation to each other for providing precise measurement of bone gap and distraction of bone in a controlled manner. Additionally, the control mechanism of the present invention includes applying direct and/or measured/graduated separation force between the two surfaces and able to deliver haptic and sensor-based feedback to the surgeon for the critical ligament tensioning and balancing aspects of the procedure.
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公开(公告)号：US07768299B2
公开(公告)日：2010-08-03
申请号：US11832128
申请日：2007-08-01
申请人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译： 提出了用于耐压漂浮N阱电路的方法和装置。 提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。 该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。 该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。
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公开(公告)号：US20060214276A1
公开(公告)日：2006-09-28
申请号：US11436452
申请日：2006-05-18
申请人： Tauseef Kazi , Jeff Gemar , Vaishnav Srinivas , Vivek Mohan
发明人： Tauseef Kazi , Jeff Gemar , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H01L23/02
CPC分类号： G01R31/3008 , G01R31/318505 , G01R31/318533
摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.
摘要翻译： 主模具和堆叠模具包括在相同的组件封装中。 在主管芯上实现传输门（370），并且能够在主管芯和堆叠管芯之间的连接（318）中接收泄漏电流，并将泄漏电流传导到接合焊盘（344） 可以在包装外部访问。 因此，可以在封装模具之后测试主模具和堆叠模具之间的连接性。 传输门在高速测试和正常运行期间被禁用。 封装还可以包括多路复用器（364），其在高速测试期间被启用以在封装级别输入和输出测试信号。 方向信号用于指示测试信号是否被输入到主模具或从主模块输出。
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公开(公告)号：US08138814B2
公开(公告)日：2012-03-20
申请号：US12181655
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/017581 , H03K19/018507
摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
摘要翻译： 用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。 信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。 第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。 第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。
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