公开(公告)号：US07586344B1

公开(公告)日：2009-09-08

申请号：US11872950

申请日：2007-10-16

申请人： Richard Booth ,  Phillip Johnson ,  Zheng Chen

发明人： Richard Booth ,  Phillip Johnson ,  Zheng Chen

IPC分类号： H03B19/00

CPC分类号： G06F1/06 ,  H03K21/406

摘要： In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

摘要翻译： 在一个实施例中，本发明可以是具有一个或多个时钟处理电路的时钟发生电路，每个时钟处理电路输出具有可调相位的时钟信号。 每个时钟处理电路包括除法器和除数控制电路。 每个除法器将输入时钟信号除以相应的除数值，并输出相应的输出时钟信号，其周期由除数值和输入时钟信号的周期确定。 每个分频器从相应的除数控制电路接收相应的除数值，其中选择除数值以便为相应的输出时钟信号实现期望的频率和相位。 临时改变除数值可以提前或延迟对应的输出时钟信号的相位，而不必复位分频器。

公开(公告)号：US08164499B1

公开(公告)日：2012-04-24

申请号：US12813540

申请日：2010-06-11

申请人： Richard Booth ,  Paulius Mosinskis ,  Phillip Johnson ,  David Onimus

发明人： Richard Booth ,  Paulius Mosinskis ,  Phillip Johnson ,  David Onimus

IPC分类号： H03M1/00

CPC分类号： H03M1/662 ,  H03M1/747

摘要： In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

摘要翻译： 在串行器/解串器（SerDes）接收器的示例性判决反馈均衡器（DFE）中，单个电流镜阵列由多个当前数模转换器（IDAC）功能共享。 DFE具有初始放大器级，其将初始系数COEFF0应用于输入数据信号和将附加系数（例如，COEFF1-COEFF5）应用于恢复的输出数据的不同延迟版本的（例如，五个）附加放大器级 流。 将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复（CDR）电路的均衡数据信号。 由于均衡器功能的某些特性，可以使用单个共享电流镜阵列实现多个附加放大器级，与传统实现相比，其保留了大量的芯片面积，其中每个附加放大器级具有其自己的专用电流镜阵列。

公开(公告)号：US07521969B2

公开(公告)日：2009-04-21

申请号：US11494862

申请日：2006-07-28

申请人： Richard Booth ,  Phillip Johnson

发明人： Richard Booth ,  Phillip Johnson

IPC分类号： H03K19/094

CPC分类号： H03K19/018528 ,  H03K19/094

摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.

摘要翻译： 本文公开了提供改进的I / O技术的系统和方法。 例如，根据本发明的实施例，集成电路包括接收数据信号并基于数据信号提供输出信号的驱动器，驱动器具有多个具有第一组多个晶体管的晶体管， 适于提供作为输出信号的第一逻辑值的晶体管和适于基于数据信号提供第二逻辑值作为输出信号的多个晶体管的第二组。 排序电路将数据信号提供给驱动器，使得多个晶体管的第一组在多个晶体管的第二组关断之前被接通，并且多个晶体管的第二组在之前被接通 关闭多个晶体管的第一组。

公开(公告)号：US08441292B1

公开(公告)日：2013-05-14

申请号：US12813573

申请日：2010-06-11

申请人： Phillip Johnson ,  Richard Booth ,  Paulius Mosinskis

发明人： Phillip Johnson ,  Richard Booth ,  Paulius Mosinskis

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03M9/00

摘要： In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

摘要翻译： 在一个实施例中，通过在反序列化之前一次选择性地滑动一个或多个输入串行数据流一比特来对齐多个（串行器/解串器）SERDES通道。 在每个SERDES通道内，滑动电路通过延长对应的时钟信号的占空比的高部分，将对应的串行数据流滑移一位（即，一个单位间隔（UI））。 时钟信号的高部分使用3对1多路复用器进行扩展，其选择固定的高信号，例如高电源轨，作为中间多路复用器输出信号，无论何时在两个不同的施加时钟信号之间进行转换 另一个用户界面。 以这种方式，滑动电路可以避免由两个时钟信号之间直接切换引起的毛刺。

公开(公告)号：US20080024171A1

公开(公告)日：2008-01-31

申请号：US11494862

申请日：2006-07-28

申请人： Richard Booth ,  Phillip Johnson

发明人： Richard Booth ,  Phillip Johnson

IPC分类号： H03K19/094

CPC分类号： H03K19/018528 ,  H03K19/094

摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.

摘要翻译： 本文公开了提供改进的I / O技术的系统和方法。 例如，根据本发明的实施例，集成电路包括接收数据信号并基于数据信号提供输出信号的驱动器，驱动器具有多个具有第一组多个晶体管的晶体管， 适于提供作为输出信号的第一逻辑值的晶体管和适于基于数据信号提供第二逻辑值作为输出信号的多个晶体管的第二组。 排序电路将数据信号提供给驱动器，使得多个晶体管的第一组在多个晶体管的第二组关断之前被接通，并且多个晶体管的第二组在之前被接通 关闭多个晶体管的第一组。

公开(公告)号：US20120279030A1

公开(公告)日：2012-11-08

申请号：US13549334

申请日：2012-07-13

申请人： Jeffery Sheldon ,  Richard Booth ,  Ken Bueche

发明人： Jeffery Sheldon ,  Richard Booth ,  Ken Bueche

IPC分类号： A61F2/06 ,  D04C1/06 ,  D06C7/00 ,  D03D3/02 ,  D03D41/00

CPC分类号： A61F2/885 ,  A61F2/06 ,  A61F2/844 ,  A61F2/86 ,  A61F2/90 ,  A61F2/91 ,  A61F2/915 ,  A61F2/95 ,  A61F2/966 ,  A61F2002/061 ,  A61F2002/91591 ,  A61F2002/9534 ,  A61F2002/9665 ,  A61F2210/0014 ,  A61F2220/0058 ,  B23K26/20 ,  B23K26/244 ,  B23K2101/32 ,  B23K2103/14 ,  D03D3/02 ,  D04C1/06 ,  D06C7/00 ,  D10B2509/00 ,  D10B2509/06 ,  Y10T29/49849

摘要： A woven, self-expanding stent device has one or more strands and is configured for insertion into an anatomical structure. The device includes a coupling structure secured to two different strand end portions that are substantially aligned with each other. The two different strand end portions include nickel and titanium. The coupling structure is not a strand of the device.

公开(公告)号：US20080010765A1

公开(公告)日：2008-01-17

申请号：US11820484

申请日：2007-06-19

申请人： Richard Booth

发明人： Richard Booth

IPC分类号： B08B9/027 ,  B21D39/00

CPC分类号： E21B37/02 ,  Y10T29/49826

摘要： A cleaning device connectable to a downhole tool for use within a well bore, the cleaning device comprising: a base member non-rotatably mountable to the downhole tool; and at least one sleeve member rotatably mountable to and around the base member, the sleeve member having a support member and at least one protruding member which protrudes from the support member and which, in use, contacts an inner surface of the well bore, wherein the support member comprises a bearing material.

摘要翻译： 一种可连接到井下工具以用于井眼内的清洁装置，所述清洁装置包括：不可旋转地安装到所述井下工具的基座构件; 以及至少一个套筒构件，其可旋转地安装到所述基座构件周围并且围绕所述基座构件，所述套筒构件具有支撑构件和至少一个从所述支撑构件突出并且在使用中与所述井筒的内表面接触的突出构件，其中 支撑构件包括轴承材料。

公开(公告)号：US20070068670A1

公开(公告)日：2007-03-29

申请号：US11586611

申请日：2006-10-26

申请人： Richard Booth

发明人： Richard Booth

IPC分类号： E21B37/02

CPC分类号： E21B37/02

摘要： A downhole tool for conditioning a casing or liner. The tool includes blades having a a circumferential peripheral edge for 360 degree contact with the casing or liner and are formed from a composite material which comprises a polymeric fibre. Such polymeric fibres include Kevlar®, Twaron®, Dyneema®, Spectra® and Diolen®. Bypass channels for fluid flow past the tool are provided in either the tool body or the blades.

摘要翻译： 用于调节套管或衬管的井下工具。 该工具包括具有与壳体或衬套360度接触的圆周周缘的刀片，并且由包含聚合物纤维的复合材料形成。 这种聚合物纤维包括Kevlar，Dyna，Spectra和Diolen。 用于流过工具的流体流动的旁路通道设置在工具主体或刀片中。

公开(公告)号：US20060227895A1

公开(公告)日：2006-10-12

申请号：US11442488

申请日：2006-05-26

申请人： Richard Booth ,  Stephan Schell ,  Thomas Biedka ,  Paul Liang

发明人： Richard Booth ,  Stephan Schell ,  Thomas Biedka ,  Paul Liang

IPC分类号： H04L27/00 ,  H04L25/03

CPC分类号： H04L25/03866

摘要： This invention, generally speaking, modifies pulse amplitude modulated signals to reduce the ratio of average power to minimum power. The signal is modified in such a manner that the signal quality remains acceptable. The signal quality is described in terms of the Power Spectral Density (PSD) and the Error Vector Magnitude (EVM).

摘要翻译： 本发明一般地说是修改脉冲幅度调制信号以减小平均功率与最小功率的比值。 信号被修改为使得信号质量保持可接受的方式。 根据功率谱密度（PSD）和误差矢量幅度（EVM）来描述信号质量。

公开(公告)号：US20060124972A1

公开(公告)日：2006-06-15

申请号：US11339540

申请日：2006-01-26

申请人： Richard Booth ,  Donald Dazzo

发明人： Richard Booth ,  Donald Dazzo

IPC分类号： H01L29/768

CPC分类号： H01L23/5225 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cross-fill metal fill pattern technique is provided such that portions of a metal fill pattern are patterned to accomplish a secondary function. For instance, in the exemplary embodiments, ever other trace or line of interdigitated fingers is routed to a ground, while the interceding traces or lines of interdigitated fingers are routed to a power supply. In this way, a capacitor function is formed across the power supply, providing additional decoupling for the power supply. Moreover, a suitably tight cross-fill metal fill pattern (i.e., higher density of metal) provides an electrical shielding function for electromagnetic radiation passing therethrough.

摘要翻译： 提供交叉填充金属填充图案技术，使得金属填充图案的部分被图案化以实现次要功能。 例如，在示例性实施例中，交叉指状的指状物的任何其他迹线或线路被路由到地面，而交错迹线或交叉指状物线路由到电源。 以这种方式，跨电源形成电容器功能，为电源提供额外的去耦。 此外，适当紧密的交叉填充金属填充图案（即，较高的金属密度）为通过其中的电磁辐射提供电屏蔽功能。