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1.发明授权Method for mitigating adverse processor loading in a personal computer implementation of a wireless local area network adapter 有权用于减轻无线局域网适配器的个人计算机实现中的不利处理器负载的方法公开(公告)号：US08296455B2
公开(公告)日：2012-10-23
申请号：US11839152
申请日：2007-08-15
IPC分类号： G06F15/16
CPC分类号： H04L43/16 , H04L43/0894
摘要： A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions. Conversely, latency introduced by WLAN specific processing tasks during peak periods of network traffic may cause unacceptable delays to the other processes and applications requiring microprocessor attention. In addition to its primary stated purpose of allowing WLAN mobile stations to save power, this technique will use power save polling as a method for controlling delivery of network packets when the host is heavily loaded or when peak interrupt latencies make reliable packet delivery difficult or impossible.
摘要翻译： 个人计算机（PC）微处理器用于提供实现无线局域网（WLAN）适配器所需的物理层（PHY）和媒体访问控制（MAC）处理功能。 这种技术使用与WLAN协议的功率节省（PS）功能相关联的轮询机制来减轻主机处理系统上的网络压力。 它同时保持网络完整性和数据包传输。 WLAN协议轮询机制用于在网络流量和/或主处理器加载的高峰期期间短暂禁止从WLAN接入点（AP）传送数据包。 由于通常在现有适配器上的专用硬件中实现的调制，解调和MAC功能在主机PC微处理器上运行的软件中实现，所以其他主机系统进程和应用程序可能会干扰这些时间关键功能。 相反，由网络流量高峰期的WLAN特定处理任务引入的延迟可能会对需要微处理器注意的其他进程和应用程序造成不可接受的延迟。 除了主要规定的允许WLAN移动台节省电力的目的之外，该技术还将使用省电轮询作为在主机严重加载时控制网络分组传送的方法，或者当峰值中断延迟使得可靠的分组传送困难或不可能时 。
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2.发明申请Method for Mitigating Adverse Processor Loading in a Personal Computer Implementation of a Wireless Local Area Network Adapter 审中-公开一种减轻无线局域网适配器个人计算机不利处理器加载的方法公开(公告)号：US20100208612A1
公开(公告)日：2010-08-19
申请号：US12772268
申请日：2010-05-03
IPC分类号： H04L12/26
CPC分类号： H04L43/16 , H04L43/0894
摘要： A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions. Conversely, latency introduced by WLAN specific processing tasks during peak periods of network traffic may cause unacceptable delays to the other processes and applications requiring microprocessor attention. In addition to its primary stated purpose of allowing WLAN mobile stations to save power, this technique will use power save polling as a method for controlling delivery of network packets when the host is heavily loaded or when peak interrupt latencies make reliable packet delivery difficult or impossible.
摘要翻译： 个人计算机（PC）微处理器用于提供实现无线局域网（WLAN）适配器所需的物理层（PHY）和媒体访问控制（MAC）处理功能。 该技术使用与WLAN协议的功率节省（PS）功能相关联的轮询机制来减轻主机处理系统上的网络压力。 它同时保持网络完整性和数据包传输。 WLAN协议轮询机制用于在网络流量和/或主处理器加载的高峰期期间短暂禁止从WLAN接入点（AP）传送数据包。 由于通常在现有适配器上的专用硬件中实现的调制，解调和MAC功能在主机PC微处理器上运行的软件中实现，所以其他主机系统进程和应用程序可能会干扰这些时间关键功能。 相反，由网络流量高峰期的WLAN特定处理任务引入的延迟可能会对需要微处理器注意的其他进程和应用程序造成不可接受的延迟。 除了主要规定的允许WLAN移动台节省电力的目的之外，该技术还将使用省电轮询作为在主机严重加载时控制网络分组传送的方法，或者当峰值中断延迟使得可靠的分组传送困难或不可能时 。
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3.发明授权Method for mitigating adverse processor loading in a personal computer implementation of a wireless local area network adapter 有权用于减轻无线局域网适配器的个人计算机实现中的不利处理器负载的方法公开(公告)号：US07788397B1
公开(公告)日：2010-08-31
申请号：US10625799
申请日：2003-07-23
CPC分类号： H04L43/16 , H04L43/0894
摘要： A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions. Conversely, latency introduced by WLAN specific processing tasks during peak periods of network traffic may cause unacceptable delays to the other processes and applications requiring microprocessor attention. In addition to its primary stated purpose of allowing WLAN mobile stations to save power, this technique will use power save polling as a method for controlling delivery of network packets when the host is heavily loaded or when peak interrupt latencies make reliable packet delivery difficult or impossible.
摘要翻译： 个人计算机（PC）微处理器用于提供实现无线局域网（WLAN）适配器所需的物理层（PHY）和媒体访问控制（MAC）处理功能。 该技术使用与WLAN协议的功率节省（PS）功能相关联的轮询机制来减轻主机处理系统上的网络压力。 它同时保持网络完整性和数据包传输。 WLAN协议轮询机制用于在网络流量和/或主处理器加载的高峰期期间短暂禁止从WLAN接入点（AP）传送数据包。 由于通常在现有适配器上的专用硬件中实现的调制，解调和MAC功能在主机PC微处理器上运行的软件中实现，所以其他主机系统进程和应用程序可能会干扰这些时间关键功能。 相反，由网络流量高峰期的WLAN特定处理任务引入的延迟可能会对需要微处理器注意的其他进程和应用程序造成不可接受的延迟。 除了主要规定的允许WLAN移动台节省电力的目的之外，该技术还将使用省电轮询作为在主机严重加载时控制网络分组传送的方法，或者当峰值中断延迟使得可靠的分组传送困难或不可能时 。
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4.发明授权Method for minimizing time critical transmit processing for a personal computer implementation of a wireless local area network adapter 有权用于最小化无线局域网适配器的个人计算机实现的时间关键传输处理的方法公开(公告)号：US07269153B1
公开(公告)日：2007-09-11
申请号：US10442606
申请日：2003-05-21
IPC分类号： H04Q7/24
CPC分类号： H04W52/0229 , H04L25/03834 , Y02D70/142 , Y02D70/144
摘要： A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the microprocessor within the personal computer to pre-compute the time critical PHY waveforms required to respond to received packets. For instance, the acknowledge (ACK) waveform required to respond to a received WLAN packet is pre-computed and stored in the PC memory. Upon receipt of a valid packet, the samples of the ACK waveform are transferred from the PC memory to a digital to analog converter (DAC). The DAC generates the transmit waveform required for the radio modulator. By pre-computing the transmit waveform samples, the required loading on the PC microprocessor is reduced during time critical periods.
摘要翻译： 个人计算机（PC）微处理器用于提供实现无线局域网（WLAN）适配器所需的物理层（PHY）和媒体访问控制（MAC）处理功能。 该技术使用个人计算机内的微处理器来预先计算响应接收到的数据包所需的时间关键PHY波形。 例如，响应所接收的WLAN分组所需的确认（ACK）波形被预先计算并存储在PC存储器中。 在接收到有效分组时，将ACK波形的样本从PC存储器传送到数模转换器（DAC）。 DAC产生无线电调制器所需的发射波形。 通过预先计算发送波形采样，PC微处理器上的所需负载在时间关键期间减少。
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5.发明授权Method for minimizing receive packet processing for a personal computer implementation of a wireless local area network adapter 有权用于使无线局域网适配器的个人计算机实现的接收分组处理最小化的方法公开(公告)号：US07577122B1
公开(公告)日：2009-08-18
申请号：US10460684
申请日：2003-06-12
IPC分类号： H04W4/00
CPC分类号： H04L27/0012 , H04L27/2602 , H04L27/2647
摘要： A method and wireless local area network (WLAN) adapter for the reduction of receive packet processing in a communications system receiver. The method includes establishing a set of criteria which identifies a packet as one requiring demodulation. The method further includes detecting a packet preamble to trigger at least one waveform identification function and determining with the at least one waveform identification function of the detected packet meets an established criteria for demodulation. The established criteria may include at least one of data rate, modulation type, signal to noise ratio, or coding rate. If the detected packet meets the established criteria for demodulation, a host processor may be interrupted to begin demodulation.
摘要翻译： 一种用于减少通信系统接收机中的接收分组处理的方法和无线局域网（WLAN）适配器。 该方法包括建立一组标准，该标准将分组标识为需要解调的分组。 该方法还包括检测分组前导码以触发至少一个波形识别功能，并且利用检测到的分组的至少一个波形识别功能确定满足已建立的解调标准。 所建立的标准可以包括数据速率，调制类型，信噪比或编码率中的至少一个。 如果检测到的分组满足已建立的用于解调的标准，则主机处理器可能被中断以开始解调。
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6.再颁专利Method for minimizing time critical transmit processing for a personal computer implementation of a wireless local area network adapter 有权用于最小化无线局域网适配器的个人计算机实现的时间关键传输处理的方法公开(公告)号：USRE43322E1
公开(公告)日：2012-04-24
申请号：US12558409
申请日：2009-09-11
IPC分类号： H04W4/00
CPC分类号： H04W52/0229 , H04L25/03834 , Y02D70/142 , Y02D70/144
摘要： A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the microprocessor within the personal computer to pre-compute the time critical PHY waveforms required to respond to received packets. For instance, the acknowledge (ACK) waveform required to respond to a received WLAN packet is pre-computed and stored in the PC memory. Upon receipt of a valid packet, the samples of the ACK waveform are transferred from the PC memory to a digital to analog converter (DAC). The DAC generates the transmit waveform required for the radio modulator. By pre-computing the transmit waveform samples, the required loading on the PC microprocessor is reduced during time critical periods.
摘要翻译： 个人计算机（PC）微处理器用于提供实现无线局域网（WLAN）适配器所需的物理层（PHY）和媒体访问控制（MAC）处理功能。 该技术使用个人计算机内的微处理器来预先计算响应接收到的数据包所需的时间关键PHY波形。 例如，响应所接收的WLAN分组所需的确认（ACK）波形被预先计算并存储在PC存储器中。 在接收到有效分组时，将ACK波形的样本从PC存储器传送到数模转换器（DAC）。 DAC产生无线电调制器所需的发射波形。 通过预先计算发送波形采样，PC微处理器上的所需负载在时间关键期间减少。
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7.发明授权Transceiver including reactive termination for enhanced cross-modulation performance and related methods 有权收发器包括用于增强交叉调制性能的反应式终端和相关方法公开(公告)号：US06785324B1
公开(公告)日：2004-08-31
申请号：US09426847
申请日：1999-10-26
IPC分类号： H04B138
摘要： A full-duplex radio transceiver includes a transmitter and a receiver. A duplexer is connected to an output of the transmitter and an input of the receiver. The receiver includes a low noise amplifier having a nonlinear portion capable of generating undesired cross-modulation signals based upon a portion of the transmit signal coupled thereto from the duplexer and a signal from another adjacent transmitter. A bandpass filter is connected to an output of the low noise amplifier, and at least one downconverter stage is connected to an output of the bandpass filter. A reactive termination circuit is connected between the low noise amplifier and the bandpass filter for changing an impedance presented to the output of the low noise amplifier with respect to signals from the colocated transmitter to thereby reduce undesired cross-modulation signals.
摘要翻译： 全双工无线电收发器包括发射机和接收机。 双工器连接到发射器的输出端和接收器的输入端。 接收机包括具有非线性部分的低噪声放大器，该非线性部分能够基于从双工器耦合到其上的发射信号的一部分和来自另一相邻发射机的信号产生不期望的交叉调制信号。 带通滤波器连接到低噪声放大器的输出，并且至少一个下变频器级连接到带通滤波器的输出端。 反相终端电路连接在低噪声放大器和带通滤波器之间，用于相对于来自共定位发射机的信号改变呈现给低噪声放大器的输出的阻抗，从而减少不期望的交叉调制信号。
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公开(公告)号：US6018270A
公开(公告)日：2000-01-25
申请号：US884635
申请日：1997-06-27
IPC分类号： H03D7/14 , H03F1/30 , H03F3/19 , H03F3/45 , H01L21/465
CPC分类号： H03F3/45089 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F1/302 , H03D2200/0025 , H03D2200/0043 , H03F2200/453 , H03F2203/45311 , H03F2203/45374 , H03F2203/45464 , H03F2203/45508 , H03F2203/45544 , H03F2203/45596 , H03F2203/45702
摘要： A single bias block for a single or multiple low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers with compensation for temperature and integrated circuit process parameters. The power supply may be a lower voltage without sacrificing the dynamic range of the amplifier and/or mixer by applying full power supply voltage to the load with the bias applied to the base circuit through an operational amplifier and/or buffer circuit. For the mixer, a lower noise figure may also be realized by moving the gain control impedance from the emitter to the collector circuit. The circuits may be discrete components or part of an integrated circuit. Methods are disclosed for reducing the power supply voltage without affecting the dynamic range of an amplifier, for temperature and process parameter compensation, and for controlling the gain of a mixer without affecting input or output impedance.
摘要翻译： 单个偏置块用于单个或多个低压RF电路，包括一个或多个放大器和一个或多个单或双平衡混频器，具有温度补偿和集成电路工艺参数。 通过通过运算放大器和/或缓冲电路施加到基极电路的偏压，通过向负载施加全部电源电压，电源可以是较低的电压，而不会牺牲放大器和/或混频器的动态范围。 对于混频器，也可以通过将增益控制阻抗从发射极移动到集电极电路来实现较低的噪声系数。 电路可以是分立元件或集成电路的一部分。 公开了用于降低电源电压的方法，而不影响放大器的动态范围，用于温度和工艺参数补偿，以及用于控制混频器的增益而不影响输入或输出阻抗。
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公开(公告)号：US5809410A
公开(公告)日：1998-09-15
申请号：US90617
申请日：1993-07-12
CPC分类号： H03F3/45089 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F1/302 , H03D2200/0025 , H03D2200/0043 , H03F2200/453 , H03F2203/45311 , H03F2203/45374 , H03F2203/45464 , H03F2203/45508 , H03F2203/45544 , H03F2203/45596 , H03F2203/45702
摘要： A single bias block for a single or multiple low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers with compensation for temperature and integrated circuit process parameters. The power supply may be a lower voltage without sacrificing the dynamic range of the amplifier and/or mixer by applying full power supply voltage to the load with the bias applied to the base circuit through an operational amplifier and/or buffer circuit. For the mixer, a lower noise figure may also be realized by moving the gain control impedance from the emitter to the collector circuit. The circuits may be discrete components or part of an integrated circuit. Methods are disclosed for reducing the power supply voltage without affecting the dynamic range of an amplifier, for temperature and process parameter compensation, and for controlling the gain of a mixer without affecting input or output impedance.
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