公开(公告)号：US5023773A

公开(公告)日：1991-06-11

申请号：US154740

申请日：1988-02-10

申请人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  David R. Page ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  David R. Page ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

CPC分类号： G06F9/468 ,  G06F12/1483

摘要： A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

公开(公告)号：US4979098A

公开(公告)日：1990-12-18

申请号：US535248

申请日：1990-06-08

申请人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Ronald M. Smith ,  Julian Thomas

发明人： Richard I. Baum ,  Terry L. Borden ,  Justin R. Butwell ,  Carl E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Ronald M. Smith ,  Julian Thomas

IPC分类号： G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/14

CPC分类号： G06F9/468 ,  G06F12/0292 ,  G06F12/1036 ,  G06F12/1483

摘要： A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE. The results of the ART process are stored in an ART lookaside buffer (ALB) which stores the results of ART while valid for later use.

摘要翻译： 提供了一种方法和装置，用于将访问寄存器的内容转换为用于执行多个虚拟地址空间的寻址功能的信息。 访问寄存器表示系统的完整寻址能力，但不直接包含寻址信息。 该系统具有多个通用寄存器，与通用寄存器相关联的多个访问寄存器，具有由访问寄存器的内容寻址的访问列表条目的访问列表，用于保存地址空间数第二表条目的存储器存储 ASTE），其中访问列表条目的内容定位ASTE，并且ASTE包含当与通用寄存器的内容组合时将虚拟地址翻译所需的寻址信息。 访问注册翻译（ART）包括通过使用访问列表条目和ASTE来确定寻址信息的过程。 ART处理的结果存储在ART后视缓冲器（ALB）中，其存储ART的结果，有效期以后使用。

公开(公告)号：US5220669A

公开(公告)日：1993-06-15

申请号：US732936

申请日：1991-07-19

申请人： Richard I. Baum ,  Terry L. Borden ,  Carol E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Casper A. Scalzi ,  Richard J. Schmalz

发明人： Richard I. Baum ,  Terry L. Borden ,  Carol E. Clark ,  Alan G. Ganek ,  James Lum ,  Michael G. Mall ,  Casper A. Scalzi ,  Richard J. Schmalz

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/30054 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/468

摘要： A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

摘要翻译： 计算机系统具有通用寄存器，控制寄存器和访问寄存器，用于包含允许地址空间能力的信息。 链接堆栈在程序调用和程序返回操作期间使用受保护的地址空间来存储状态信息。 链接堆栈包含与保存的信息的状态条目相关的信息，以及指向其他链接堆栈部分的报头和尾部条目。 控制寄存器包含指向当前链接堆栈条目的指针，并在程序调用或返回移动通过堆栈时更改。

公开(公告)号：US4843541A

公开(公告)日：1989-06-27

申请号：US79314

申请日：1987-07-29

申请人： George H. Bean ,  Terry L. Borden ,  Mark S. Farrell ,  Peter H. Gum ,  Roger E. Hough ,  Francis E. Johnson ,  Donald W. McCauley ,  Mark E. Rakhmilevich ,  John C. Rathjen ,  Casper A. Scalzi ,  John F. Scanlon ,  Leslie W. Wyman

发明人： George H. Bean ,  Terry L. Borden ,  Mark S. Farrell ,  Peter H. Gum ,  Roger E. Hough ,  Francis E. Johnson ,  Donald W. McCauley ,  Mark E. Rakhmilevich ,  John C. Rathjen ,  Casper A. Scalzi ,  John F. Scanlon ,  Leslie W. Wyman

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10

CPC分类号： G06F9/4843 ,  G06F9/5077

摘要： The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems. The logical CPU(s) of the guests are dispatched on one or plural real CPUs in the system using the S/370XA SIE (start interpretive execution) instruction. Special operations are provided, including the CPU alerting of other guests in different partitions using I/O interruption signalling. Interception is provided to handle special circumstances.

公开(公告)号：US5495606A

公开(公告)日：1996-02-27

申请号：US148091

申请日：1993-11-04

申请人： Terry L. Borden ,  William K. Kelley ,  Iderpal S. Narang ,  Bharat D. Rathi ,  David J. Wisneski

发明人： Terry L. Borden ,  William K. Kelley ,  Iderpal S. Narang ,  Bharat D. Rathi ,  David J. Wisneski

IPC分类号： G06F15/173 ,  G06F17/30 ,  G06F15/17

CPC分类号： G06F17/30445 ,  G06F15/17375 ,  Y10S707/99933

摘要： A parallel query processing system comprises a front end processor, a query processing complex attached to the front end processor, and a database on a data repository attached by a first path to the front end processor, and by one or more additional paths to one or more slave processors within the query processing complex. An external operations command processor within the front end processor quiesces database managers in the slave processors to permit maintenance operations by the front end processor, and restarts the slave processors in read-only mode after maintenance operation completion. A splitter/scheduler function in a master processor within the query processor complex receives complex read-only queries from the front end processor, splits them into query elements, schedules the query elements for execution on the slave processors and recombines the execution results to be sent back to the front end processor.

摘要翻译： 并行查询处理系统包括前端处理器，连接到前端处理器的查询处理复合体，以及数据库，由通过第一路径附加到前端处理器的数据库，以及通过一个或多个附加路径到一个或多个 更多的从属处理器内的查询处理复杂。 前端处理器中的外部操作命令处理器使从属处理器中的数据库管理器停止，以允许前端处理器进行维护操作，并在维护操作完成后以只读模式重新启动从属处理器。 查询处理器中的主处理器中的分离器/调度器功能从前端处理器接收复杂的只读查询，将其分解为查询元素，调度查询元素以便在从属处理器上执行，并重新组合要发送的执行结果 回到前端处理器。