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1.发明授权System for parallel processing of complex read-only database queries using master and slave central processor complexes 失效使用主从中央处理器复合的并行处理复杂的只读数据库查询的系统
公开(公告)号：US5495606A
公开(公告)日：1996-02-27
申请号：US148091
申请日：1993-11-04
IPC分类号： G06F15/173 , G06F17/30 , G06F15/17
CPC分类号： G06F17/30445 , G06F15/17375 , Y10S707/99933
摘要： A parallel query processing system comprises a front end processor, a query processing complex attached to the front end processor, and a database on a data repository attached by a first path to the front end processor, and by one or more additional paths to one or more slave processors within the query processing complex. An external operations command processor within the front end processor quiesces database managers in the slave processors to permit maintenance operations by the front end processor, and restarts the slave processors in read-only mode after maintenance operation completion. A splitter/scheduler function in a master processor within the query processor complex receives complex read-only queries from the front end processor, splits them into query elements, schedules the query elements for execution on the slave processors and recombines the execution results to be sent back to the front end processor.
摘要翻译： 并行查询处理系统包括前端处理器，连接到前端处理器的查询处理复合体，以及数据库，由通过第一路径附加到前端处理器的数据库，以及通过一个或多个附加路径到一个或多个 更多的从属处理器内的查询处理复杂。 前端处理器中的外部操作命令处理器使从属处理器中的数据库管理器停止，以允许前端处理器进行维护操作，并在维护操作完成后以只读模式重新启动从属处理器。 查询处理器中的主处理器中的分离器/调度器功能从前端处理器接收复杂的只读查询，将其分解为查询元素，调度查询元素以便在从属处理器上执行，并重新组合要发送的执行结果 回到前端处理器。
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2.发明授权
公开(公告)号：US5313609A
公开(公告)日：1994-05-17
申请号：US704553
申请日：1991-05-23
IPC分类号： G06F12/08 , G06F15/16 , G06F15/177 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/082
摘要： A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global directory associated with the main memory to keep track of state and control information of cache lines. Upon a request by a requesting cache for a cache line which has been exclusively modified by a source cache, two buffers are situated in the global directory to collectively intercept modified data words of the modified cache line during the write-back to memory. A modified word buffer is used to capture modified words within the modified cache line. Moreover, a line buffer stores an old cache line transferred from the memory, during the write back operation. Finally, the line buffer and the modified word buffer, together, provide the entire modified line to a requesting cache.
摘要翻译： 提供了一种基于目录的协议，用于在具有多个处理器的多处理（MP）系统中维持数据一致性，该处理器具有相关联的回写高速缓存，通向共享存储器的多级互连网络（MIN），以及与 主存储器来跟踪缓存行的状态和控制信息。 在请求高速缓存针对由源高速缓存专门修改的高速缓存行的请求时，两个缓冲器位于全局目录中以在回写到存储器期间共同拦截修改的高速缓存线的修改数据字。 修改后的字缓冲区用于捕获修改后的高速缓存行中的修改字。 此外，在回写操作期间，行缓冲器存储从存储器传送的旧高速缓存行。 最后，行缓冲区和修改后的字缓冲区一起，将整个修改后的行提供给请求缓存。
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公开(公告)号：US4813044A
公开(公告)日：1989-03-14
申请号：US9166
申请日：1987-01-30
申请人： Manoj Kumar , Ambuj Goyal , Bharat D. Rathi
发明人： Manoj Kumar , Ambuj Goyal , Bharat D. Rathi
CPC分类号： G06F11/0751 , G06F11/14
摘要： A method and apparatus used to detect errors in a signal transmitted over a single wire. All transient errors are detected when the effect of the transient lasts for at least one cycle and not more than five cycles. Transient errors of longer duration will be detected if the level of the original signal at the start of the transient is different from that at the end of the transient. Stuck faults will be deleted if one onset of the stuck fault causes the level of the signal to change. Redundancy is incorporated by introducing redundant transitions in the signal on the same wire. This requires the successive transitions in the original signal to be at least three cycles apart. If a transition is viewed as a binary one and the absence of a transition as a binary zero then each binary one is replaced with the sequence "one-one-one" (overwriting subsequent zeros), and keeping each zero as the single bit "zero". Upon decoding, each group of three transitions is converted to a single transition. Signals having more than or less than three consecutive transitions which are not in multiples of three are determined to be in error.
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4.发明授权公开(公告)号：US07016309B1
公开(公告)日：2006-03-21
申请号：US09547959
申请日：2000-04-12
IPC分类号： H04L12/26
CPC分类号： H04L43/0835
摘要： A method and apparatus for accurately calculating packet loss along a communication channel using data in a pair of measuring packets is disclosed. The invention calculates packet loss between a first and second node over a communication circuit. A first known quantity of packets is communicated from the first node to the second node at a first known time. A first actual count of packets received by the second node from the first known quantity of packets is then determined. A second known quantity of packets is then communicated from the first node to the second node at a second known time. A second actual count of packets received by the second node from the second known quantity of packets is then determined. The difference between the first known quantity of packets communicated at the first known time and the second known quantity of packets communicated at the second known time is calculated to obtain a value for “packets sent”. The difference between the first actual count of packets received and the second actual count of packets received is calculated to obtain a value for “packets received”. The difference between the packets sent and the packets received provides a value for “packet loss” between the first known time and second known time.
摘要翻译： 公开了一种使用一对测量分组中的数据精确地计算沿通信信道的分组丢失的方法和装置。 本发明通过通信电路计算第一和第二节点之间的分组丢失。 第一已知数量的分组在第一已知时间从第一节点传送到第二节点。 然后确定第二节点从第一已知数量的分组接收的分组的第一实际计数。 然后在第二已知时间将第二已知数量的数据包从第一节点传送到第二节点。 然后确定第二节点从第二已知数量的分组接收的分组的第二实际计数。 计算在第一已知时间传送的第一已知数量的分组与在第二已知时间传送的第二已知数量的分组之间的差异，以获得“发送分组”的值。 计算接收的分组的第一实际计数与接收的分组的第二实际计数之间的差异，以获得“接收到的分组”的值。 所发送的分组与接收的分组之间的差异在第一已知时间和第二已知时间之间提供“分组丢失”的值。
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5.发明授权Hardware mechanism for automatically detecting hot-spot references and diverting same from memory traffic in a multiprocessor computer system 失效用于自动检测热点参考并将其从多处理器计算机系统中的存储器流量转移的硬件机制
公开(公告)号：US4969088A
公开(公告)日：1990-11-06
申请号：US186327
申请日：1988-04-26
IPC分类号： G06F15/167 , G06F12/12 , G06F13/16 , G06F15/173 , H04L12/56
CPC分类号： H04L45/28 , G06F12/122 , G06F13/1663 , G06F15/17393 , H04L45/00 , H04L45/24
摘要： An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within the second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.
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6.发明授权Data processing system incorporating a memory resident directive for synchronizing multiple tasks among plurality of processing elements by monitoring alternation of semaphore data 失效数据处理系统包括存储器驻留指令，用于通过监视信号量数据的交替来同步多个处理元件中的多个任务
公开(公告)号：US4965718A
公开(公告)日：1990-10-23
申请号：US250673
申请日：1988-09-29
申请人： David A. George , Bharat D. Rathi
发明人： David A. George , Bharat D. Rathi
摘要： In a data processing system of the type including a plurality of processing elements interconnected with each other and with a plurality of memory elements by an interconnection means, a method is provided for accommodating the accessing of a selected memory location in a selected one of the memory elements by at least one requesting processing element to read data stored thereat. The method thereby permits the communication of information between the plurality of processing elements. The method comprising the steps of: sending, from the requesting processing element to the selected memory element via the interconnecting means, a directive including (1) the address of the selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending the directive; reading in the selected memory element the data stored at the selected memory location; comparing in the memory element the read data with the comparison value; notifying the requesting processing element via the interconnection means if the read data matches the comparison value; storing the directive in the selected memory element if the read data does not match the comparison value; and repeating the reading, comparing, and notifying steps each time the data in the selected memory location is altered.
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