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    Semiconductor device with isolation trench liner
    1.
    发明授权
    Semiconductor device with isolation trench liner 有权
    半导体器件带隔离沟槽衬垫

    公开(公告)号：US08716828B2

    公开(公告)日：2014-05-06

    申请号：US13473175

    申请日：2012-05-16

    申请人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    发明人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76232

    摘要： A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

    摘要翻译： 半导体器件包括其中限定有活性晶体管区域的半导体材料层，形成在与有源晶体管区域相邻的半导体材料中的隔离沟槽和衬在隔离沟槽上的沟槽衬垫，其中沟槽衬垫由材料形成， 基本上禁止在其上形成高k材料，并且其中隔离沟槽和沟槽衬里一起形成衬里的沟槽。 该器件在衬里沟槽中具有绝缘材料，并且高k栅极材料覆盖绝缘材料的至少一部分并且覆盖有源晶体管区域的至少一部分，使得沟槽衬垫将高k 栅极材料覆盖绝缘材料的至少一部分与覆盖有源晶体管区域的至少一部分的高k栅极材料。

    Semiconductor device with isolation trench liner
    2.
    发明授权
    Semiconductor device with isolation trench liner 有权
    半导体器件带隔离沟槽衬垫

    公开(公告)号：US08217472B2

    公开(公告)日：2012-07-10

    申请号：US13178362

    申请日：2011-07-07

    申请人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    发明人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    IPC分类号： H01L29/772

    CPC分类号： H01L21/76232

    摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

    摘要翻译： 这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。 该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。 然后用绝缘材料填充衬里的沟槽。 此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。 衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

    Integrated circuit having long and short channel metal gate devices and method of manufacture
    3.
    发明授权
    Integrated circuit having long and short channel metal gate devices and method of manufacture 有权
    具有长和短沟道金属栅极器件的集成电路及其制造方法

    公开(公告)号：US07902599B2

    公开(公告)日：2011-03-08

    申请号：US12607710

    申请日：2009-10-28

    申请人： Richard J. Carter ,  Michael J. Hargrove ,  George J. Kluth ,  John G. Pellerin

    发明人： Richard J. Carter ,  Michael J. Hargrove ,  George J. Kluth ,  John G. Pellerin

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/823468 ,  H01L29/4933 ,  H01L29/66545

    摘要： Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the SC device, and is formed substantially from the same metal as is the LC metal gate.

    摘要翻译： 提供集成电路的实施例。 在一个实施例中，集成电路包括衬底，短沟道（SC）器件和长沟道（LC）器件。 短沟道器件包括覆盖衬底的第一部分的SC栅极绝缘体，覆盖SC栅极绝缘体的SC金属栅极，覆盖在金属栅极上的多晶硅层和形成在多晶硅层上的硅化物层。 长沟道（LC）器件包括覆盖衬底的第二部分的LC栅极绝缘体和覆盖LC栅极绝缘体的LC金属栅极。 蚀刻停止层覆盖在衬底的上表面上，并且层间电介质覆盖在蚀刻停止层的上表面上。 SC盖设置在层间电介质中，覆盖SC器件，并且基本上由与LC金属栅极相同的金属形成。

    SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER, AND RELATED FABRICATION METHODS
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER, AND RELATED FABRICATION METHODS 有权
    具有隔离衬板的半导体器件及相关制造方法

    公开(公告)号：US20100052094A1

    公开(公告)日：2010-03-04

    申请号：US12199616

    申请日：2008-08-27

    申请人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    发明人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    IPC分类号： H01L29/00 ,  H01L21/76

    CPC分类号： H01L21/76232

    摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

    摘要翻译： 这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。 该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。 然后用绝缘材料填充衬里的沟槽。 此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。 衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

    Integrated circuit long and short channel metal gate devices and method of manufacture
    5.
    发明授权
    Integrated circuit long and short channel metal gate devices and method of manufacture 有权
    集成电路长短通道金属栅极器件及其制造方法

    公开(公告)号：US07723192B2

    公开(公告)日：2010-05-25

    申请号：US12048414

    申请日：2008-03-14

    申请人： Richard J. Carter ,  Michael J. Hargrove ,  George J. Kluth ,  John G. Pellerin

    发明人： Richard J. Carter ,  Michael J. Hargrove ,  George J. Kluth ,  John G. Pellerin

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/823468 ,  H01L29/4933 ,  H01L29/66545

    摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

    摘要翻译： 提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。 在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。 金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。

    Semiconductor device with isolation trench liner, and related fabrication methods
    6.
    发明授权
    Semiconductor device with isolation trench liner, and related fabrication methods 有权
    具有隔离沟槽衬垫的半导体器件及相关制造方法

    公开(公告)号：US07998832B2

    公开(公告)日：2011-08-16

    申请号：US12199616

    申请日：2008-08-27

    申请人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    发明人： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76232

    摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

    摘要翻译： 这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。 该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。 然后用绝缘材料填充衬里的沟槽。 此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。 衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

    Methods for fabricating MOS devices having highly stressed channels
    7.
    发明授权
    Methods for fabricating MOS devices having highly stressed channels 有权
    制造具有高应力通道的MOS器件的方法

    公开(公告)号：US07767534B2

    公开(公告)日：2010-08-03

    申请号：US12240682

    申请日：2008-09-29

    申请人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    发明人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L29/66636

    摘要： Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

    摘要翻译： 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，沉积覆盖栅电极的应力诱导层，退火含硅衬底以重结晶 栅电极，去除应力诱导层，使用栅电极作为蚀刻掩模蚀刻到衬底中的凹槽，以及在凹槽中外延生长杂质掺杂的含硅区域。

    Method of controlling floating body effects in an asymmetrical SOI device
    8.
    发明授权
    Method of controlling floating body effects in an asymmetrical SOI device 有权
    控制非对称SOI器件浮体效应的方法

    公开(公告)号：US06756637B2

    公开(公告)日：2004-06-29

    申请号：US09899957

    申请日：2001-07-06

    申请人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    发明人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    IPC分类号： H01L2976

    CPC分类号： H01L29/78612 ,  H01L21/26586

    摘要： High performance asymmetric transistors including controllable diode characteristics at the source and/or drain are developed by supplying impurities with high accuracy of location by angled implants in a trench or diffusion from a solid body formed as a sidewall of doped material. High concentration gradient of impurities to support high performance is achieved by providing for reduced heat treatment after the impurity is supplied in order to limit diffusion previously necessary to achieve the desired location of impurity structures. Damascene or quasi-Damascene gate structures are also provided for high dimensional uniformity, increased manufacturing yield and structural integrity of the transistor.

    摘要翻译： 在源极和/或漏极处包括可控二极管特性的高性能不对称晶体管通过在沟槽中的倾斜注入提供高精度的杂质或从形成为掺杂材料的侧壁的固体的扩散而开发。 通过在提供杂质之后提供减少的热处理以便限制先前必需的扩散以实现杂质结构的所需位置来实现高浓度梯度的杂质以支持高性能。 还提供了大马士革或准大马士革门结构，用于高尺寸均匀性，增加的制造产量和晶体管的结构完整性。

    Methods for fabricating MOS devices having highly stressed channels
    10.
    发明授权
    Methods for fabricating MOS devices having highly stressed channels 有权
    制造具有高应力通道的MOS器件的方法

    公开(公告)号：US08076209B2

    公开(公告)日：2011-12-13

    申请号：US12771948

    申请日：2010-04-30

    申请人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    发明人： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L29/66636

    摘要： Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

    摘要翻译： 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，使用栅电极作为蚀刻掩模将凹陷蚀刻到衬底中，沉积应力诱导 覆盖栅极电极，退火含硅衬底以使栅电极重结晶，去除应力诱导层，以及在凹槽中外延生长杂质掺杂的含硅区域。