公开(公告)号：US07941577B2

公开(公告)日：2011-05-10

申请号：US12139063

申请日：2008-06-13

申请人： Richard L. Arndt ,  Patrick A. Buckland ,  Harvey G. Kiel ,  Renato J. Recio ,  Jaya Srikrishnan

发明人： Richard L. Arndt ,  Patrick A. Buckland ,  Harvey G. Kiel ,  Renato J. Recio ,  Jaya Srikrishnan

IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F9/34

CPC分类号： G06F9/45537

摘要： A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

摘要翻译： 一种方法，计算机程序产品和分布式数据处理系统，其允许多系统映像虚拟服务器内的系统映像将其相关系统存储器的一部分或全部直接暴露给共享PCI适配器，而无需经过可信任的 组件，如Hypervisor。 具体地，本发明涉及用于共享常规PCI I / O适配器，PCI-X I / O适配器，PCI-Express I / O适配器的机制，并且一般地，使用使用存储器映射的任何I / O适配器 I / O接口进行通讯。

公开(公告)号：US07681083B2

公开(公告)日：2010-03-16

申请号：US12105955

申请日：2008-04-18

申请人： Richard L. Arndt ,  Patrick A. Buckland ,  Gregory M. Nordstrom ,  Steven M. Thurber

发明人： Richard L. Arndt ,  Patrick A. Buckland ,  Gregory M. Nordstrom ,  Steven M. Thurber

IPC分类号： G06F11/00

CPC分类号： G06F11/2736

摘要： Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

摘要翻译： 用于在数据处理系统中隔离输入/输出适配器错误域的方法，装置和系统。 在一个输入/输出适配器中发生的错误与数据处理系统的其他输入/输出适配器隔离，主机桥中的功能将输入/输出适配器连接到数据处理系统的系统总线，从而允许使用低 成本，行业标准交换机和主桥外部的桥梁。

公开(公告)号：US20080082706A1

公开(公告)日：2008-04-03

申请号：US11536745

申请日：2006-09-29

申请人： Patrick A. Buckland ,  Philip M. Corcoran ,  Edward J. Seminaro

发明人： Patrick A. Buckland ,  Philip M. Corcoran ,  Edward J. Seminaro

IPC分类号： G06F13/00

CPC分类号： G06F13/4226 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods, systems and computer products for SCSI power control, data flow and addressing. Exemplary embodiments include a SCSI system having a SCSI bus with a plurality of data lines, including a first repeater configuration, a second repeater configuration, a method for selectively enabling at least one of the first and second repeater configurations and a method for selectively assigning SCSI IDs on devices on a SCSI bus.

摘要翻译： 用于SCSI功率控制，数据流和寻址的方法，系统和计算机产品。 示例性实施例包括具有多个数据线的SCSI总线的SCSI系统，包括第一中继器配置，第二中继器配置，用于选择性地启用第一和第二中继器配置中的至少一个的方法以及用于选择性地分配SCSI SCSI总线上设备上的ID。

公开(公告)号：US08645746B2

公开(公告)日：2014-02-04

申请号：US12959917

申请日：2010-12-03

申请人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

发明人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

IPC分类号： G06F11/00

CPC分类号： G06F13/4068 ,  G06F11/2007 ,  G06F11/2017 ,  G06F2201/85

摘要： Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.

摘要翻译： 提供了用于为第一PCIE桥和第一输入/输出（IO）设备之间的连接提供故障切换操作的方法和装置。 使用第一PCIE桥的第一组通道，通过第一链路在第一PCIE桥和第一IO设备之间交换第一组总线位。 响应于检测到第一链路中的故障，使用连接第二PCIE桥和第二IO设备的第二链路的未使用部分，在第一PCIE桥与第一IO设备之间交换第一组总线位。

公开(公告)号：US08677176B2

公开(公告)日：2014-03-18

申请号：US12959981

申请日：2010-12-03

申请人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

发明人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

IPC分类号： G06F11/00

CPC分类号： G06F11/2005 ,  G06F11/2007 ,  G06F13/4022 ,  G06F2213/0026

摘要： Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.

公开(公告)号：US5555390A

公开(公告)日：1996-09-10

申请号：US375064

申请日：1995-01-19

申请人： Ian D. Judd ,  Patrick A. Buckland ,  Roger G. Cath ,  Gordon J. Cockburn ,  William A. Short

发明人： Ian D. Judd ,  Patrick A. Buckland ,  Roger G. Cath ,  Gordon J. Cockburn ,  William A. Short

IPC分类号： G06F3/06 ,  G06F13/12 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F2003/0697

摘要： A data storage subsystem and method for transferring data from a storage subsystem to a connected host data processing system are described. The subsystem comprises a device controller connected to one or more direct access storage devices e.g. disk drives. The host data processing system issues data transfer commands to the subsystem to initiate transfer of data between the host processing system and the device(s) associated with the data storage subsystem. Read/write data is transferred directly from device to host via a buffer controller. For a read operation, the read command from the host data processing system specifies the data to be transferred and the start address in host memory to which the data should be sent. The device controller of the data storage subsystem is capable of respecifying or amending the start address specified by the host in the rad command. This provides a performance bonefit for split data transfers. In addition, if an error occurs during a read operation, the device controller of the data storage subsystem can specify the host address to which the replacement data should be sent.

摘要翻译： 描述了用于将数据从存储子系统传送到连接的主机数据处理系统的数据存储子系统和方法。 子系统包括连接到一个或多个直接访问存储设备的设备控制器，例如 磁盘驱动器 主机数据处理系统向子系统发出数据传送命令以发起主机处理系统与与数据存储子系统相关联的设备之间的数据传输。 读/写数据通过缓冲控制器直接从设备传输到主机。 对于读取操作，来自主机数据处理系统的读取命令指定要传送的数据和要发送数据的主机存储器中的起始地址。 数据存储子系统的设备控制器能够在rad命令中重新指定或修改主机指定的起始地址。 这为分割数据传输提供了一个性能骨干。 另外，如果在读取操作期间发生错误，则数据存储子系统的设备控制器可以指定应该发送替换数据的主机地址。

公开(公告)号：US4833596A

公开(公告)日：1989-05-23

申请号：US172042

申请日：1988-03-23

申请人： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

发明人： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

IPC分类号： G06F3/153 ,  G09G5/22

CPC分类号： G06F3/153 ,  G09G5/222 ,  G09G2360/04

摘要： A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be "windowed" onto the display device when it is assigned to the main processor. In the fourth mode, a display assigned to the co-processor displays data being run by code that is written to the displayed on a display device with a different pel resolution. The main processor does a pel conversion operation on the data in the process of transferring the data from the virtual buffer to the real buffer.

摘要翻译： 一种用于控制数据处理系统中的数据显示的方法和系统，所述数据处理系统包括主处理器，存储器子系统和输入/输出子系统，所述子系统包括用于在I / O总线上管理业务的I / O通道控制器，所述I / O通道控制器具有 附加协处理器和多个I / O设备，包括具有不同保留I / O地址空间的显示设备。 主处理器可以为具有不同保留的I / O地址空间的显示器建立不同的显示模式，这通常表示不同的显示类型。 在一种模式中，显示器专门分配给主处理器，并且协同处理器对该显示器的数据传输进行了尝试。 在第二模式中，通过在主存储器中建立虚拟视频缓冲器，在另一个处理器对显示设备进行控制时，由一个处理器写入显示器，在处理器之间进行时间共享。 每当将显示器重新分配给另一个处理器时，虚拟和实际缓冲区的内容将被交换。 在第三模式中，虚拟缓冲器中的协处理器数据在分配给主处理器时可以被“窗口化”到显示设备上。 在第四模式中，分配给协处理器的显示器以不同的像素分辨率显示正被写入显示设备上的代码运行的数据。 在将数据从虚拟缓冲器传送到实际缓冲器的过程中，主处理器对数据执行像素转换操作。

公开(公告)号：US20080165490A1

公开(公告)日：2008-07-10

申请号：US11621178

申请日：2007-01-09

申请人： Patrick A. Buckland ,  Ray C. Laning ,  Thoi Nguyen ,  Kenneth R. Peters ,  Edward J. Seminaro ,  Rebeccah J. Vossberg

发明人： Patrick A. Buckland ,  Ray C. Laning ,  Thoi Nguyen ,  Kenneth R. Peters ,  Edward J. Seminaro ,  Rebeccah J. Vossberg

IPC分类号： G06F1/16

CPC分类号： G06F1/187 ,  G11B33/128

摘要： A computer chassis is provided that may accommodate direct access storage device cages for various form factors. A 3.5-inch direct access storage device (DASD) cage may support 3.5-inch serial attached SCSI (SAS) direct access storage devices. The 3.5-inch SAS DASD cage includes a DASD backplane with a main connector and eight SAS drive connectors. A SFF direct access storage device cage may support SFF SAS direct access storage devices. The SFF SAS DASD cage may include a DASD backplane with a main connector and two port expanders. The port expanders may support up to twelve SAS DASD with redundant SAS channel wiring and one external 4-channel SAS port.

摘要翻译： 提供了一种计算机机箱，其可容纳用于各种形状因素的直接存取设备保持架。 3.5英寸直接存取存储设备（DASD）机箱可能支持3.5英寸串行连接SCSI（SAS）直接存取设备。 3.5英寸SAS DASD机箱包括一个带主连接器和8个SAS驱动器连接器的DASD背板。 SFF直接访问存储设备机箱可以支持SFF SAS直接访问存储设备。 SFF SAS DASD机箱可能包括带有主连接器和两个端口扩展器的DASD背板。 端口扩展器可以支持多达12个SAS DASD，冗余SAS通道接线和一个外部4通道SAS端口。

公开(公告)号：US4757441A

公开(公告)日：1988-07-12

申请号：US68769

申请日：1987-06-29

申请人： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

发明人： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

IPC分类号： G06F3/153 ,  G09G5/22 ,  G06F13/10 ,  G06F15/16

CPC分类号： G09G5/222 ,  G06F3/153 ,  G09G2360/04

摘要： A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that have been made to the virtual buffer.

摘要翻译： 一种用于控制数据处理系统中的数据显示的方法和系统，所述数据处理系统包括主处理器，存储器子系统和输入/输出子系统，所述子系统包括用于在I / O总线上管理业务的I / O通道控制器，所述I / O通道控制器具有 附加协处理器和多个I / O设备，包括具有不同保留I / O地址空间的显示设备。 主处理器可以为具有不同保留的I / O地址空间的显示器建立不同的显示模式，这通常表示不同的显示类型。 在一种模式中，显示器专门分配给主处理器，并且协同处理器对该显示器的数据传输进行了尝试。 显示控制装置基于与协处理器相关联的逻辑电路，用于捕获具有在为显示设备保留的范围内的地址的指令。 根据主处理器建立的模式，该逻辑使得能够将视频缓冲区的正常写入和读取抑制或重新定位到虚拟缓冲区。 在存储器中建立循环队列以使得主处理器能够随着对虚拟缓冲器的改变而选择性地单独地更新视频缓冲器。