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    Cable redundancy and failover for multi-lane PCI express IO interconnections
    2.
    发明授权
    Cable redundancy and failover for multi-lane PCI express IO interconnections 失效

    公开(公告)号：US08677176B2

    公开(公告)日：2014-03-18

    申请号：US12959981

    申请日：2010-12-03

    申请人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

    发明人： Patrick A. Buckland ,  Jay R. Herring ,  Gregory M. Nordstrom ,  William A. Thompson

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2005 ,  G06F11/2007 ,  G06F13/4022 ,  G06F2213/0026

    摘要： Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.

    Interrupt source controller with scalable state structures
    3.
    发明授权
    Interrupt source controller with scalable state structures 有权
    具有可扩展状态结构的中断源控制器

    公开(公告)号：US08549202B2

    公开(公告)日：2013-10-01

    申请号：US12850008

    申请日：2010-08-04

    申请人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steve Thurber

    发明人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steve Thurber

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.

    摘要翻译： 数据处理系统包括耦合到处理器核心的处理器核心，系统存储器，其包括包括与多个中断中的相应一个中断相关联的多个条目的中断数据结构。 包括至少一个I / O主机桥和多个可分割端点（PE）的输入/输出（I / O）子系统，每一个具有相关联的PE号码。 I / O主机桥响应于接收至少包括消息地址的消息信号中断（MSI），从消息地址确定中断数据结构中的多个条目中的特定条目的系统存储器地址，访问 特定条目，并且基于特定条目的内容，验证中断源的授权以发出MSI并呈现与特定条目相关联的用于服务的中断。

    PROVIDING VIRTUAL FUNCTIONS AFTER AN INPUT/OUTPUT ADAPTER IS MOVED FROM A FIRST LOCATION TO A SECOND LOCATION
    5.
    发明申请
    PROVIDING VIRTUAL FUNCTIONS AFTER AN INPUT/OUTPUT ADAPTER IS MOVED FROM A FIRST LOCATION TO A SECOND LOCATION 失效
    输入/输出适配器从第一个位置移动到第二个位置后提供虚拟功能

    公开(公告)号：US20120191884A1

    公开(公告)日：2012-07-26

    申请号：US13013460

    申请日：2011-01-25

    申请人： Sean T. Brownlow ,  Bryan M. Logan ,  Gregory M. Nordstrom ,  John R. Oberly, III

    发明人： Sean T. Brownlow ,  Bryan M. Logan ,  Gregory M. Nordstrom ,  John R. Oberly, III

    IPC分类号： G06F13/12

    CPC分类号： G06F13/385

    摘要： A computer implemented method includes identifying a hardware input/output adapter in a first physical slot location. The computer implemented method includes determining that the hardware input/output adapter is capable of hosting a plurality of virtual functions in the first physical slot location. The computer implemented method also includes selecting a group identifier that is unassociated with another physical slot location. The computer implemented method includes associating the group identifier with the first physical slot location of the hardware input/output adapter.

    摘要翻译： 计算机实现的方法包括在第一物理槽位置中识别硬件输入/输出适配器。 计算机实现的方法包括确定硬件输入/输出适配器能够在第一物理时隙位置托管多个虚拟功能。 计算机实现的方法还包括选择与另一个物理槽位置不相关的组标识符。 计算机实现的方法包括将组标识符与硬件输入/输出适配器的第一物理槽位置相关联。

    ADDRESS TRANSLATION TABLE TO ENABLE ACCESS TO VIRTUALIZED FUNCTIONS
    6.
    发明申请
    ADDRESS TRANSLATION TABLE TO ENABLE ACCESS TO VIRTUALIZED FUNCTIONS 有权
    地址翻译表可以访问虚拟化功能

    公开(公告)号：US20120151471A1

    公开(公告)日：2012-06-14

    申请号：US12962841

    申请日：2010-12-08

    申请人： Sean T. Brownlow ,  Gregory M. Nordstrom ,  Travis J. Pizel

    发明人： Sean T. Brownlow ,  Gregory M. Nordstrom ,  Travis J. Pizel

    IPC分类号： G06F9/455

    CPC分类号： G06F12/0292 ,  G06F9/4411 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45579

    摘要： A computer-implemented method may include assigning an address translation table to a peripheral component interconnect host bridge and determining that an input/output adapter accessible to the peripheral component interconnect host bridge is configured as a virtualized adapter to provide a plurality of virtual functions to a plurality of logical partitions. In response to determining that the input/output adapter is configured as the virtualized adapter, the address translation table may be subdivided to enable the plurality of virtual functions to access the memory of at least one logical partition of the plurality of logical partitions.

    摘要翻译： 计算机实现的方法可以包括将地址转换表分配给外围组件互连主机桥并且确定外围组件互连主机桥可访问的输入/输出适配器被配置为虚拟适配器以向多个虚拟功能提供多个虚拟功能 多个逻辑分区。 响应于确定输入/输出适配器被配置为虚拟化适配器，地址转换表可以被细分，以使多个虚拟功能能够访问多个逻辑分区中的至少一个逻辑分区的存储器。

    MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION FOR VIRTUAL BRIDGES
    7.
    发明申请
    MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION FOR VIRTUAL BRIDGES 失效
    内存映射输入/输出总线地址范围用于虚拟桥的翻译

    公开(公告)号：US20110296074A1

    公开(公告)日：2011-12-01

    申请号：US12787799

    申请日：2010-05-26

    申请人： Gregory M. Nordstrom ,  Steven M. Thurber ,  Curtis C. Wollbrink

    发明人： Gregory M. Nordstrom ,  Steven M. Thurber ,  Curtis C. Wollbrink

    IPC分类号： G06F13/40

    CPC分类号： G06F13/404 ,  G06F2213/0058

    摘要： In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

    摘要翻译： 在一个实施例中，南芯片包括连接到共享出口的第一虚拟桥和还连接到共享出口的第二虚拟桥。 第一虚拟桥接器从第一北芯片接收第一辅助总线标识符，第一从属总线标识符和第一MMIO总线地址范围。 第二虚拟桥从第二北芯片接收第二副总线标识符，第二从属总线标识符和第二MMIO总线地址范围。 第一虚拟桥存储第一副总线标识符，第一下级总线标识符和第一MMIO总线地址范围。 第二虚拟桥存储第二副总线标识符，第二从属总线标识符和第二MMIO总线地址范围。 第一北芯片和第二北芯片通过相应的第一和第二点对点连接连接到南芯片。

    PHYSICAL TO HIERARCHICAL BUS TRANSLATION
    8.
    发明申请
    PHYSICAL TO HIERARCHICAL BUS TRANSLATION 有权
    物理到分层总线翻译

    公开(公告)号：US20110252167A1

    公开(公告)日：2011-10-13

    申请号：US12758329

    申请日：2010-04-12

    申请人： William J. Armstrong ,  Scott N. Dunham ,  David R. Engebretsen ,  Gregory M. Nordstrom ,  Steven M. Thurber ,  Curtis C. Wollbrink ,  Adalberto G. Yanes

    发明人： William J. Armstrong ,  Scott N. Dunham ,  David R. Engebretsen ,  Gregory M. Nordstrom ,  Steven M. Thurber ,  Curtis C. Wollbrink ,  Adalberto G. Yanes

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4027

    摘要： In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip.

    摘要翻译： 在一个实施例中，将物理总线编号转换为分层总线编号被写入到南芯片。 南芯片接收包含物理总线号码的配置写命令。 南芯片通过物理总线标识的总线将配置写命令发送到设备，设备将物理总线号存储在设备中。 响应于来自包括物理总线号码的设备的接收到的消息，南芯片用分层总线号代替消息中的物理总线号码。 南芯片通过点对点串行链路将消息发送到北芯片。 物理总线编号和分层总线数字都标识了一个总线，设备连接到南芯片的一个桥。

    Independent computer storage addressing in input/output transfers
    9.
    发明授权
    Independent computer storage addressing in input/output transfers 失效
    输入/输出传输中独立的计算机存储寻址

    公开(公告)号：US5634007A

    公开(公告)日：1997-05-27

    申请号：US398053

    申请日：1995-03-02

    申请人： Salvatore A. Calta ,  Robert B. Cook ,  Fernando A. Luiz ,  Gregory M. Nordstrom ,  Martin W. Sachs ,  Caryl A. Thorn

    发明人： Salvatore A. Calta ,  Robert B. Cook ,  Fernando A. Luiz ,  Gregory M. Nordstrom ,  Martin W. Sachs ,  Caryl A. Thorn

    IPC分类号： G06F13/28 ,  G06F12/06

    CPC分类号： G06F13/28

    摘要： A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

    摘要翻译： 一种用于通过为每个设备预先存储逻辑令牌和设备可识别的偏移值作为标记来识别一个或多个本地存储器地址内的一个或多个本地存储器地址的方式和装置，用于在请求者和响应器设备之间执行直接存储器地址（DMA）操作 所述设备，以及由所述请求者设备在所述请求者设备中向所述应答器设备发送所述令牌和偏移值的DMA操作，所述响应者设备通过所述令牌和偏移值的转换来识别响应者设备本地存储器地址，以及所述应答器设备 访问识别的响应者本地存储器地址用于与令牌和偏移相关联的数据传输，以及请求者设备标识用于完成数据传输的请求者设备本地存储器地址。