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12 条记录 (耗时 0.084 秒)

    Signal coupler with automatic common line attenuation compensation
    6.
    发明授权
    Signal coupler with automatic common line attenuation compensation 失效
    具有自动公共线衰减补偿的信号耦合器

    公开(公告)号：US5627501A

    公开(公告)日：1997-05-06

    申请号：US417374

    申请日：1995-04-05

    申请人： Bernard Biran ,  Peter P. F. Reusens

    发明人： Bernard Biran ,  Peter P. F. Reusens

    IPC分类号： H04L5/06 ,  H04M11/06 ,  H03H7/46

    CPC分类号： H04M11/062 ,  H04L5/06 ,  H04Q2213/13034 ,  H04Q2213/1319 ,  H04Q2213/13199 ,  H04Q2213/13302 ,  H04Q2213/13305 ,  H04Q2213/1332

    摘要： The present invention relates to a for coupling Plain Old Telephone Service (POTS) signals and Asymmetric Digital Subscriber Line (ADSL) signals to a common line (TL). In order to avoid saturation of inductances (L1,L2,L3,L4) of a low pass POTS filter (LPF) located between the POTS transmitter/receiver (PTR) and this common line (TL) when the POTS signal is not sufficiently attenuated by this common line (TL), a variable impedance (SL) is inserted between the POTS transmitter/receiver (PTR) and this low pass POTS filter (LPF). The value of this variable impedance (SL) is controlled by a control signal (CS) supplied by the ADSL transmitter/receiver (ATR) which measures the attenuation caused by this common line (TL).

    摘要翻译： 本发明涉及将普通老式电话业务（POTS）信号和非对称数字用户线路（ADSL）信号耦合到公共线路（TL）。 为了避免当POTS信号没有充分衰减时位于POTS发射机/接收机（PTR）和该公共线路（TL）之间的低通POTS滤波器（LPF）的电感（L1，L2，L3，L4）饱和 通过该公共线（TL），在POTS发射器/接收器（PTR）和该低通POTS滤波器（LPF）之间插入可变阻抗（SL）。 该可变阻抗（SL）的值由由测量由该公共线（TL）引起的衰减的ADSL发射机/接收机（ATR）提供的控制信号（CS）控制。

    Decoder device for decoding convolutionally encoded message
    7.
    发明授权
    Decoder device for decoding convolutionally encoded message 失效
    用于解码卷积编码消息的解码器装置

    公开(公告)号：US5331665A

    公开(公告)日：1994-07-19

    申请号：US878731

    申请日：1992-05-05

    申请人： Hans J. J. Busschaert ,  Peter P. F. Reusens ,  Ronny M. A. Van Camp

    发明人： Hans J. J. Busschaert ,  Peter P. F. Reusens ,  Ronny M. A. Van Camp

    IPC分类号： H04L25/08 ,  H03M13/23 ,  H03M13/41 ,  H03D1/00 ,  G06F11/10 ,  H03M13/12 ,  H04L27/06

    CPC分类号： H03M13/41

    摘要： A decoder device (VD) used for decoding digital messages according to the Viterbi convolutional decoding algorithm. This Viterbi decoder (VD) may be integrated in a portion of a single electronic chip for inclusion in a receiver of a handportable mobile station of a digital cellular radio system. The decoder (VD) includes a first module (VITALFA) to calculate transition probabilities for the possible state transitions between two successive states of the decoder, and a second module (VIPROB) to calculate, as a function of the state transition probabilities, path probabilities for the possible paths constituted by successive state transitions and ending in each of these states, and to select the path having the highest path probability value. The first/second module (VITALFA/VIPROB) of the device (VD) further calculates a state transition/path bit error rate which is function of the difference between the bits (softbits) received in the first module (VITALFA) and the bits (coded bits) expected for a same state transition/path respectively.

    摘要翻译： 用于根据维特比卷积解码算法解码数字消息的解码器装置（VD）。 该维特比解码器（VD）可以集成在单个电子芯片的一部分中，以包含在数字蜂窝无线电系统的手持移动台的接收机中。 解码器（VD）包括第一模块（VITALFA），用于计算解码器的两个连续状态之间的可能状态转换的转换概率，以及第二模块（VIPROB），以根据状态转移概率来计算路径概率 对于由连续状态转换构成的可能路径并且以这些状态中的每一个结束，并选择具有最高路径概率值的路径。 设备（VD）的第一/第二模块（VITALFA / VIPROB）还计算状态转换/路径误码率，其是在第一模块（VITALFA）中接收的比特（软比特）与比特 编码比特）分别预期相同的状态转换/路径。

    Digital filter and multi-channel decimator
    8.
    发明授权
    Digital filter and multi-channel decimator 失效
    数字滤波器和多通道抽取器

    公开(公告)号：US5262970A

    公开(公告)日：1993-11-16

    申请号：US760770

    申请日：1991-09-16

    申请人： Joannes M. J. Sevenhans ,  Peter P. F. Reusens ,  Lajos Kiss

    发明人： Joannes M. J. Sevenhans ,  Peter P. F. Reusens ,  Lajos Kiss

    IPC分类号： H03H17/02 ,  H03H17/06 ,  G06F15/31

    CPC分类号： H03H17/0607 ,  H03H17/0621 ,  H03H17/0664 ,  H03H2218/06

    摘要： A multi-sample multi-channel digital decimator filter producing a Finite Impulse filtering Response (FIR) from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. each from 1,024 kHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 Read Only Memory modules (0, 1, 2, 3). The Read Only Memory modules are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) being able to cycle through 4 distinct conditions. The 4 adder accumulators (ACC 0, 1, 2, 3) are coupled to the outputs of their respective channel multipliers. They each partially compute in parallel outputs words using one sixteenth of the coefficients and the multiplexer rotates these words, thereby enabling complete computation in 4 cycles. 4 registers (REG 00, 01, 02, 03) are associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the Read Only Memory modules.

    Digital transmission system
    9.
    发明授权
    Digital transmission system 失效
    数字传输系统

    公开(公告)号：US4803437A

    公开(公告)日：1989-02-07

    申请号：US84250

    申请日：1987-08-12

    申请人： Peter P. F. Reusens

    发明人： Peter P. F. Reusens

    IPC分类号： G06F1/025 ,  H03M1/00 ,  H04M1/50 ,  H03K3/017 ,  H03K3/02

    CPC分类号： H04M1/505 ,  G06F1/025

    摘要： A signal generator for generating a modulated output signal from a clock signal. The generator comprises a divider means which derives from the clock signal a square wave having a first fundamental frequency. Means connected to the divider means also provides from the clock signal a rectangular wave signal having a second fundamental frequency that is an even integral multiple of the first fundamental frequency. A chopper chops the square wave signal by the rectangular wave signal to provide the output signal. The frequency content of the spectrum of the output signal is the same as that of the square wave signal.

    摘要翻译： 一种用于从时钟信号产生调制输出信号的信号发生器。 该发生器包括一个从时钟信号中得到具有第一基频的方波的分频装置。 连接到除法器装置的装置还从时钟信号提供具有第二基频的矩形波信号，该第二基频是第一基频的偶数整数倍。 斩波器通过矩形波信号对方波信号进行斩波，以提供输出信号。 输出信号的频谱的频率含量与方波信号的频率含量相同。

    Converter circuit
    10.
    发明授权
    Converter circuit 失效
    转换电路

    公开(公告)号：US4733219A

    公开(公告)日：1988-03-22

    申请号：US19443

    申请日：1987-02-26

    申请人： Peter P. F. Reusens ,  Jozef D. G. L. Cannaerts

    发明人： Peter P. F. Reusens ,  Jozef D. G. L. Cannaerts

    IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M7/00 ,  H04B14/06 ,  H04Q11/04 ,  H03M7/32

    CPC分类号： H04Q11/04 ,  H03M7/304 ,  H04B14/062 ,  H03M7/3028

    摘要： A prior art digital Delta-Sigma converter is improved by including a second control loop with a second forward branch coupled between the first and second subtractor circuits and a third subtractor circuit coupled in series to the first integrator circuit and with a second feedback branch and a third subtractor circuit coupled to the output of said first integrator circuit. When the input signal is equal to zero the output signal of the first integrator circuit will rapidly change to zero because the second control loop applies an additional feedback signal to the third subtractor circuit and therefore also to the first integrator circuit. Because the output signal of the first integrator output circuit signal thus more rapidly varies to zero the same is true for the output signal of the second integrator circuit and therefore also for the converter output signal.

    摘要翻译： 通过包括耦合在第一和第二减法器电路之间的第二前向分支的第二控制回路和与第一积分器电路串联耦合的第三减法器电路以及第二反馈支路和 耦合到所述第一积分器电路的输出的第三减法器电路。 当输入信号等于零时，第一积分器电路的输出信号将迅速变为零，因为第二控制环路向第三减法器电路施加附加的反馈信号，因此也向第一积分器电路施加。 因为第一积分器输出电路信号的输出信号因此更快地变化到零，所以对于第二积分器电路的输出信号也是如此，因此也用于转换器输出信号。