公开(公告)号：US20170080607A1

公开(公告)日：2017-03-23

申请号：US14859060

申请日：2015-09-18

Applicant: Richard Sahara ,  Pat Corder ,  DeWayne Abbas

Inventor： Richard Sahara ,  Pat Corder ,  DeWayne Abbas

IPC: B29C35/08

CPC classification number: B29C35/0805 ,  B29C2035/0827 ,  F21S2/00 ,  F21Y2105/00 ,  F21Y2107/50

Abstract: A lighting system for illuminating a target area, including a substantially planar mounting surfaced disposed adjacent and substantially parallel to the plane of the target area, and a first plurality of collimated light sources mounted to the mounting surface and disposed to emit in a first orientation at a first predetermined angle from the mounting surface; wherein the plurality of light sources are arranged for overlapping illumination of a region of the target area, and the region is illuminated with substantially uniform intensity at a substantially common angle of incidence.

公开(公告)号：US06365968B1

公开(公告)日：2002-04-02

申请号：US09130742

申请日：1998-08-07

Applicant: Yi Qian ,  Hanh Lu ,  Richard Sahara

Inventor： Yi Qian ,  Hanh Lu ,  Richard Sahara

IPC: H01L2348

CPC classification number: H01S5/22 ,  H01L2224/05644 ,  H01L2224/85205 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01S5/0425 ,  H01S5/2275 ,  H01S2301/176

Abstract: An electro-optical, ridge-waveguide device and method for its fabrication utilizes a polyimide ridge-protection layer, which provides good ridge protection/planarization while minimizing parasitic capacitance. A silicon oxide interlayer is used between a metal contact layer and the polyimide. This interlayer facilitates the adhesion between the metal contact layer and the underlying device since good adhesion can be obtained between the silicon oxide layer and the polyimide layer and between the metal layer and silicon oxide layer. Preferably, the polyimide is roughened to increase the surface area contact between the polyimide layer and silicon oxide layer to further increase adhesion and thus the pull-off force required to separate the metal contact layer from the device. While such roughening can be achieved through plasma etching, in a preferred embodiment, the polyimide layer is roughened by patterned etching. Specifically, a patterned photoresist is used as a etch-protection layer to form a series of wells in the polyimide layer that have a pitch between 1 and 20 microns.

Abstract translation: 电光学，脊 - 波导器件及其制造方法利用聚酰亚胺脊保护层，其在最小化寄生电容的同时提供良好的脊保护/平坦化。 在金属接触层和聚酰亚胺之间使用氧化硅中间层。 由于在氧化硅层和聚酰亚胺层之间以及金属层和氧化硅层之间可以获得良好的粘附性，所以该中间层有助于金属接触层与下面的器件之间的粘附。 优选地，聚酰亚胺被粗糙化以增加聚酰亚胺层和氧化硅层之间的表面积接触，以进一步提高粘合性，并因此提高将金属接触层与器件分开所需的拉脱力。 尽管通过等离子体蚀刻可以实现这种粗糙化，但是在优选实施例中，通过图案化蚀刻使聚酰亚胺层变粗糙。 具体地，使用图案化的光致抗蚀剂作为蚀刻保护层，以在聚酰亚胺层中形成间距在1和20微米之间的一系列孔。

公开(公告)号：US5841151A

公开(公告)日：1998-11-24

申请号：US544088

申请日：1995-10-17

Applicant: Richard Sahara

Inventor： Richard Sahara

IPC: G02F1/025 ,  G02F1/015 ,  G02F1/017 ,  H01L27/15 ,  H01S5/00 ,  H01S5/026 ,  H01S5/042 ,  H01L29/06

CPC classification number: B82Y20/00 ,  G02F1/01725 ,  H01S5/0265 ,  G02F2001/0158 ,  G02F2001/0175 ,  G02F2001/01758

Abstract: A semiconductor device having a quantum well structure, the quantum well structure having: a first quantum well layer for forming a quantum well for electrons, the first quantum well layer having a first band structure; a second quantum well layer for forming a quantum well for holes, the second quantum well layer having a second band structure different from the first band structure; and an intermediate layer interposed between the first and second quantum well layers having a third band structure different from the first and second band structures, wherein the first quantum well layer forms a barrier to holes, and the second quantum well layer forms a barrier to electrons. Semiconductor devices having quantum well structures different from conventional type I and II quantum well structures are provided.

Abstract translation: 一种具有量子阱结构的半导体器件，所述量子阱结构具有：用于形成用于电子的量子阱的第一量子阱层，所述第一量子阱层具有第一带结构; 用于形成用于空穴的量子阱的第二量子阱层，所述第二量子阱层具有不同于所述第一带结构的第二带结构; 以及介于所述第一和第二量子阱层之间的中间层，其具有不同于所述第一和第二带结构的第三带结构，其中所述第一量子阱层形成对空穴的屏障，并且所述第二量子阱层形成对电子的屏障 。 提供了具有与常规I型和II型量子阱结构不同的量子阱结构的半导体器件。