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公开(公告)号：US20060189061A1
公开(公告)日：2006-08-24
申请号：US11407313
申请日：2006-04-19
申请人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
发明人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。
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公开(公告)号：US07411227B2
公开(公告)日：2008-08-12
申请号：US11407313
申请日：2006-04-19
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。
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公开(公告)号：US07655557B2
公开(公告)日：2010-02-02
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。
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公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。
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公开(公告)号：US20070294376A1
公开(公告)日：2007-12-20
申请号：US11471133
申请日：2006-06-20
IPC分类号： G06F15/177
CPC分类号： G06F8/61
摘要： A software provisioning model which effectively combines characteristics of both push and pull models. In response to a request, a server sends a workflow or recipe of actions along with code server parameters and a requesting client computer system executes the,workflow and pulls necessary software updates and services to the client.
摘要翻译： 一种有效地结合推拉模型的特征的软件配置模型。 响应于请求，服务器发送操作的工作流程或配方以及代码服务器参数，并且请求的客户端计算机系统执行该工作流，并向客户端提取必要的软件更新和服务。
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