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    High performance CMOS device structure with mid-gap metal gate
    5.
    发明授权
    High performance CMOS device structure with mid-gap metal gate 失效
    高性能CMOS器件结构，具有中间间隙金属栅极

    公开(公告)号：US06916698B2

    公开(公告)日：2005-07-12

    申请号：US10795672

    申请日：2004-03-08

    申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

    摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

    High performance CMOS device structure with mid-gap metal gate
    6.
    发明授权
    High performance CMOS device structure with mid-gap metal gate 失效
    高性能CMOS器件结构，具有中间间隙金属栅极

    公开(公告)号：US06762469B2

    公开(公告)日：2004-07-13

    申请号：US10127196

    申请日：2002-04-19

    申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC分类号： H01L2976

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

    摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

    Hybrid planar and finFET CMOS devices
    7.
    发明授权
    Hybrid planar and finFET CMOS devices 失效
    混合平面和finFET CMOS器件

    公开(公告)号：US06911383B2

    公开(公告)日：2005-06-28

    申请号：US10604097

    申请日：2003-06-26

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/3205

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Hybrid planar and FinFET CMOS devices
    8.
    发明授权
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US07250658B2

    公开(公告)日：2007-07-31

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/772

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Ultra-thin body super-steep retrograde well (SSRW) FET devices
    10.
    发明授权
    Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
    超薄体超陡逆行井（SSRW）FET器件

    公开(公告)号：US07002214B1

    公开(公告)日：2006-02-21

    申请号：US10710736

    申请日：2004-07-30

    申请人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

    发明人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

    摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

    摘要翻译： 超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。 掩埋氧化层。 使SOI层变薄以形成超薄SOI层。 形成将SOI层分离成N和P接地平面区域的隔离沟槽。 用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。 在N和P接地平面区域之上形成半导体沟道区。 在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。 可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。