公开(公告)号：US07655557B2

公开(公告)日：2010-02-02

申请号：US12145113

申请日：2008-06-24

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US07411227B2

公开(公告)日：2008-08-12

申请号：US11407313

申请日：2006-04-19

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L27/10 ,  H01L29/73

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20080254622A1

公开(公告)日：2008-10-16

申请号：US12145113

申请日：2008-06-24

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US07056782B2

公开(公告)日：2006-06-06

申请号：US10786901

申请日：2004-02-25

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

公开(公告)号：US06927117B2

公开(公告)日：2005-08-09

申请号：US10725851

申请日：2003-12-02

申请人： Cyril Cabral, Jr. ,  Jakub T. Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An L. Steegen

发明人： Cyril Cabral, Jr. ,  Jakub T. Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An L. Steegen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823835

摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.

摘要翻译： 提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。 本发明的集成方案使与制造包含硅化物触点和硅化物栅极金属的CMOS结构相关联的复杂性和成本最小化。

公开(公告)号：US07112481B2

公开(公告)日：2006-09-26

申请号：US11254929

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

公开(公告)号：US07067368B1

公开(公告)日：2006-06-27

申请号：US11254934

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US07064025B1

公开(公告)日：2006-06-20

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US07550338B2

公开(公告)日：2009-06-23

申请号：US11854829

申请日：2007-09-13

申请人： An L. Steegen ,  Haining S. Yang ,  Ying Zhang

发明人： An L. Steegen ,  Haining S. Yang ,  Ying Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

摘要翻译： 半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。 栅极堆叠在半导体衬底上。 应变层形成在至少一个间隙的至少一部分中。 应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

公开(公告)号：US06891192B2

公开(公告)日：2005-05-10

申请号：US10604607

申请日：2003-08-04

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg G. Gluschenkov ,  An L. Steegen ,  Haining S. Yang

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg G. Gluschenkov ,  An L. Steegen ,  Haining S. Yang

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L31/036

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。