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公开(公告)号：US06724021B2
公开(公告)日：2004-04-20
申请号：US10067205
申请日：2002-02-05
IPC分类号： H01L29745
CPC分类号： H01L29/7811 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/7802 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P). Thereby a gradual variation is achieved in the potential (V2) applied by the successive trenched field-shaping regions (40) in the peripheral area (P) of the voltage-sustaining zone (20). This advantageous peripheral termination reduces device susceptibility to deviations in the field profile in this peripheral area (P).
摘要翻译： 诸如功率MOSFET，肖特基整流器或pn整流器的半导体器件在与相应的第一和第二相对表面相邻的第一（21,23a）和第二（22）器件区域之间具有电压维持区域（20） （11,12）。包括电阻路径（42）的有沟槽的场整形区域（40）延伸通过所述电压维持区域（20）延伸到下面的第二区域（22），以便增强 器件的击穿电压。 电压维持区域（20）和沟槽场整形区域（40）存在于器件的有源器件区域（A）和外围区域（P）中。 另外的电阻通道（53）跨越第一表面（11）延伸穿过外围区域（P）。 该另外的电阻路径（53）提供了一个分压器，其连接到周边区域（P）中连续的下游沟槽场整形区域（40）的相应的电阻路径（42）。 由此，在由维持电压区（20）的周边区域（P）中的连续沟槽场整形区域（40）施加的电位（V2）中实现了逐渐变化。 这种有利的外围终端降低了该外围区域（P）中场分布偏差的装置敏感性。
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公开(公告)号：US06605862B2
公开(公告)日：2003-08-12
申请号：US10068921
申请日：2002-02-07
IPC分类号： H01L29414
CPC分类号： H01L29/405 , H01L29/408 , H01L29/41766 , H01L29/7802 , H01L29/7813 , H01L29/861
摘要： A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41). This lower level (82) is more closely aligned to the p-n junction (24) and is protected by the insulating layer (44) extending to the higher level (81). This construction enables the electric field distribution in the voltage-sustaining zone (20) to be improved by aligning very closely the start of the potential drop along the resistive path (42) with the p-n junction depth (d).
摘要翻译： 诸如MOSFET或PN二极管整流器的半导体器件在第一器件区域（23）和下伏电压维持区（20）之间具有p-n结（24）。 倾斜的场成形区域（40）延伸通过电压维持区域（20），以改善装置的压阻和导通电阻特性。 沟槽场整形区域（40）包括容纳在其侧壁上具有绝缘层（44）的沟槽（41）中的电阻路径（42）。 绝缘层（44）将电阻从电阻路径（42）介电地耦合到耗尽该器件的电压阻断模式的电压维持区（20）。 绝缘层（44）在沟槽（41）的侧壁处延伸到高于电阻路径（42）在沟槽（41）中开始的较低电平（82）的上电平（81） 。 该较低电平（82）与p-n结（24）更紧密地对准，并被延伸到较高电平（81）的绝缘层（44）保护。 这种结构使得能够通过非常接近地沿着电阻路径（42）与p-n结深度（d）非常接近的电位降的起始来提高电压维持区（20）中的电场分布。
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公开(公告)号：US07154177B2
公开(公告)日：2006-12-26
申请号：US10518267
申请日：2003-06-13
IPC分类号： H01L29/40
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/41
摘要： A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of the trenches. A conductive bridge (23) connects the surface implants (21) to allow equilibrium to be reached in reverse bias.
摘要翻译： 半导体器件具有具有多个沟槽（17）的边缘终止区域（15）。 导电材料（20）和绝缘材料（19）形成在沟槽处，并且表面植入物（21）形成在沟槽的两侧。 导电桥（23）连接表面植入物（21）以允许以反向偏压达到平衡。
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公开(公告)号：US20070222019A1
公开(公告)日：2007-09-27
申请号：US10594487
申请日：2005-03-29
IPC分类号： H01L29/36
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
摘要翻译： 与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。 通过面罩中的开口形成沟槽。 沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的 在沟槽的侧壁的顶部和沟槽的底部的硅。 硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。
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公开(公告)号：US07394144B2
公开(公告)日：2008-07-01
申请号：US10594487
申请日：2005-03-29
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336 , H01L21/764
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
摘要翻译： 与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。 通过面罩中的开口形成沟槽。 沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的 在沟槽的侧壁的顶部和沟槽的底部的硅。 硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。
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6.发明申请公开(公告)号：US20070228496A1
公开(公告)日：2007-10-04
申请号：US11574334
申请日：2005-09-01
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/66712 , H01L29/7813
摘要： A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of trenches (20) in the drift region (12) and the opposite conductivity type material is epitaxially grown from the bottom of the trenches (20). The presence of the sidewall insulating material (31) reduces the possibility of defects during the epitaxial growth and hence excessive leakage currents in the device (1). The insulating material (31) also prevents epitaxial growth on the trench sidewalls and hence substantially prevents forming voids in the trenches which would lessen the accuracy of charge compensation. The epitaxial growth by this method can be well controlled and may be stopped at an upper level (21) below the top major surface (10a). Thus, for example, trench-gates 22, 23 may be formed in the same trenches (20) above the compensation columns (30).
摘要翻译： 垂直半导体器件，例如沟槽栅MOSFET功率晶体管（1）具有一个导电类型的漂移区域（12），其包含相反导电类型的间隔的垂直列（30），用于器件击穿电压的电荷补偿增加 。 绝缘材料（31）仅设置在漂移区域（12）中的沟槽（20）的侧壁上，并且相反的导电型材料从沟槽（20）的底部外延生长。 侧壁绝缘材料（31）的存在降低了在外延生长期间的缺陷的可能性，并因此降低了器件（1）中的过大的漏电流。 绝缘材料（31）还防止沟槽侧壁上的外延生长，从而基本上防止在沟槽中形成空穴，这将降低电荷补偿的精度。 通过该方法的外延生长可以很好地控制，并且可以在顶部主表面（10a）下方的上层（21）处停止。 因此，例如，可以在补偿柱（30）上方的相同沟槽（20）中形成沟槽栅极22,23。
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公开(公告)号：US20050173776A1
公开(公告)日：2005-08-11
申请号：US10518267
申请日：2003-06-13
申请人： Rob Dalen , Christelle Rochefort
发明人： Rob Dalen , Christelle Rochefort
IPC分类号： H01L29/06 , H01L29/40 , H01L29/41 , H01L29/78 , H01L27/095
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/41
摘要： A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of the trenches. A conductive bridge (23) connects the surface implants (21) to allow equilibrium to be reached in reverse bias.
摘要翻译： 半导体器件具有具有多个沟槽（17）的边缘终止区域（15）。 导电材料（20）和绝缘材料（19）形成在沟槽处，并且表面植入物（21）形成在沟槽的两侧。 导电桥（23）连接表面植入物（21）以允许以反向偏压达到平衡。
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