公开(公告)号：US20170059303A1

公开(公告)日：2017-03-02

申请号：US14840883

申请日：2015-08-31

申请人： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Zhiyong Wang ,  Shuhong Liu ,  Pilin Liu

发明人： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Zhiyong Wang ,  Shuhong Liu ,  Pilin Liu

IPC分类号： G01B11/06

CPC分类号： G01B11/0625 ,  G01B2210/56 ,  H01L22/12

摘要： Some example forms relate to a method of nondestructively measuring a geometry of an electrical component on a substrate. The method includes directing light at the electrical component. The light is at an original intensity. The method further includes measuring light that is reflected off of the electrical component. The reflected light includes undiffracted light and diffracted light. The diffracted light is at a diffracted intensity. The method further includes determining a ratio of diffracted intensity to original intensity and utilizing the ratio to determine a geometry of the electrical component.

摘要翻译： 一些示例形式涉及非破坏性地测量衬底上的电气部件的几何形状的方法。 该方法包括将光引导到电气部件。 光线处于原始强度。 该方法还包括测量从电气部件反射的光。 反射光包括未衍射的光和衍射光。 衍射光的衍射强度。 该方法还包括确定衍射强度与原始强度的比率，并利用该比率来确定电气部件的几何形状。

公开(公告)号：US10043740B2

公开(公告)日：2018-08-07

申请号：US15208313

申请日：2016-07-12

申请人： Sri Ranga Sai Boyapati ,  Rahul N. Manepalli ,  Dilan Seneviratne ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Robert Alan May ,  Islam A. Salama

发明人： Sri Ranga Sai Boyapati ,  Rahul N. Manepalli ,  Dilan Seneviratne ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Robert Alan May ,  Islam A. Salama

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/02 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

摘要： Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

公开(公告)号：US20200105731A1

公开(公告)日：2020-04-02

申请号：US16145620

申请日：2018-09-28

申请人： Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas V. Pietambaram

发明人： Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas V. Pietambaram

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/373

摘要： The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.

公开(公告)号：US20210305108A1

公开(公告)日：2021-09-30

申请号：US16832851

申请日：2020-03-27

申请人： Robert L. Sankman ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Bharat P. Penmecha

发明人： Robert L. Sankman ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Bharat P. Penmecha

IPC分类号： H01L23/15 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48

摘要： Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.