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公开(公告)号：US20200105731A1
公开(公告)日：2020-04-02
申请号：US16145620
申请日：2018-09-28
申请人： Aleksandar Aleksov , Sri Ranga Sai Boyapati , Kristof Darmawikarta , Rahul N. Manepalli , Robert Alan May , Srinivas V. Pietambaram
发明人： Aleksandar Aleksov , Sri Ranga Sai Boyapati , Kristof Darmawikarta , Rahul N. Manepalli , Robert Alan May , Srinivas V. Pietambaram
IPC分类号： H01L25/18 , H01L23/00 , H01L23/538 , H01L23/373
摘要： The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.
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公开(公告)号：US10043740B2
公开(公告)日：2018-08-07
申请号：US15208313
申请日：2016-07-12
申请人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
发明人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
IPC分类号： H01L23/48 , H01L23/498 , H01L21/02 , H01L21/48 , H01L23/00 , H01L25/065
摘要： Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
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公开(公告)号：US20170064821A1
公开(公告)日：2017-03-02
申请号：US14840979
申请日：2015-08-31
CPC分类号： H05K1/0298 , H01L23/49822 , H01L23/49838 , H05K1/113 , H05K3/0041 , H05K3/181 , H05K3/188 , H05K3/4038 , H05K3/422 , H05K3/429 , H05K3/4644 , H05K2201/09218 , H05K2201/09372 , H05K2201/095 , H05K2201/096 , H05K2201/09654 , H05K2203/0548
摘要： Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.
摘要翻译： 一些示例形式涉及电子包装。 电子封装包括第一电介质层，其包括形成在第一电介质层的表面上的电迹线和在第一电介质层的表面上的第二电介质层。 第二电介质层包括开口。 电迹线在开口内。 电子封装包括电互连，其填充开口并且在第二电介质层的上表面上方延伸，使得电互连电连接到第一电介质层上的电迹线。
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4.发明申请公开(公告)号：US20170059303A1
公开(公告)日：2017-03-02
申请号：US14840883
申请日：2015-08-31
IPC分类号： G01B11/06
CPC分类号： G01B11/0625 , G01B2210/56 , H01L22/12
摘要： Some example forms relate to a method of nondestructively measuring a geometry of an electrical component on a substrate. The method includes directing light at the electrical component. The light is at an original intensity. The method further includes measuring light that is reflected off of the electrical component. The reflected light includes undiffracted light and diffracted light. The diffracted light is at a diffracted intensity. The method further includes determining a ratio of diffracted intensity to original intensity and utilizing the ratio to determine a geometry of the electrical component.
摘要翻译： 一些示例形式涉及非破坏性地测量衬底上的电气部件的几何形状的方法。 该方法包括将光引导到电气部件。 光线处于原始强度。 该方法还包括测量从电气部件反射的光。 反射光包括未衍射的光和衍射光。 衍射光的衍射强度。 该方法还包括确定衍射强度与原始强度的比率，并利用该比率来确定电气部件的几何形状。
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公开(公告)号：US20150179593A1
公开(公告)日：2015-06-25
申请号：US14138754
申请日：2013-12-23
IPC分类号： H01L23/00
CPC分类号： H01L24/06 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2924/10253 , H01L2924/181 , H01L2924/00
摘要： In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die and one or more of the conductive pads. The package assembly may further include a solder resist layer coupled with the die and the conductive pads, and one or more interconnects positioned at least partially within the solder resist layer and directly coupled with one or more of the conductive pads.
摘要翻译： 在实施例中，封装组件可以包括与一个或多个导电焊盘耦合的管芯。 阻挡层可以直接与管芯和导电焊盘中的一个或多个耦合。 封装组件还可以包括与管芯和导电焊盘耦合的阻焊层，以及至少部分地位于阻焊层内并直接与一个或多个导电焊盘耦合的一个或多个互连。
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公开(公告)号：US09420693B2
公开(公告)日：2016-08-16
申请号：US14490615
申请日：2014-09-18
IPC分类号： H05K1/00 , H05K1/18 , H01L21/48 , H01L23/498 , H05K1/09 , H05K1/11 , H05K3/00 , H05K3/18 , H05K3/46
CPC分类号： H01G4/33 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2924/15311 , H05K1/09 , H05K1/115 , H05K1/162 , H05K1/185 , H05K3/0017 , H05K3/188 , H05K3/4644 , H05K3/467 , H05K2201/10015
摘要： An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.
摘要翻译： 公开了一种嵌入式薄膜电容器及其制造方法。 嵌入式薄膜电容器包括由电介质层分开的两个导电板。 在实施例中，电容器封装在封装衬底内。 形成嵌入式薄膜电容器的方法包括在底板和第一迹线上形成第一绝缘层。 然后在第一绝缘层中形成第一开口以暴露底板的第一区域。 然后在第一绝缘层上和在底板的暴露的第一区域的顶部上形成粘合剂层。 通过绝缘层和第一绝缘层形成第二开口以露出底板的第二区域。 顶板形成在第一开口内，并在第二开口内形成通孔。
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