公开(公告)号：US09406747B2

公开(公告)日：2016-08-02

申请号：US14307055

申请日：2014-06-17

申请人： Robert Bosch GmbH

发明人： Heribert Weber ,  Hartmut Kueppers ,  Jens Frey ,  Neil Davies ,  Jochen Reinmuth

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L25/065 ,  H01L23/31 ,  B81C1/00 ,  H01L25/00

CPC分类号： H01L29/0657 ,  B81C1/00238 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L23/3114 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014

摘要： A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.

摘要翻译： 垂直集成的混合部件以晶片级封装的形式实现，包括：至少两个元件基板，一个彼此组装; 由电绝缘铸件制成的模制上密封层; 并且所述部件的外部电接触通过嵌入在所述密封层中的至少一个接触印模在顶侧上实现，使得（i）其下端连接到元件基板的布线层，以及（ii）其 上端暴露在密封层的表面。

公开(公告)号：US20240322033A1

公开(公告)日：2024-09-26

申请号：US18255760

申请日：2021-12-02

申请人： Robert Bosch GmbH

发明人： Dragos Costachescu ,  Neil Davies

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41725

摘要： A vertical power transistor having front and rear sides. The vertical power transistor includes a drift region that includes a first doping with a first charge carrier type, and a body region that includes a second doping with a second charge carrier type. The body region is situated on the drift region, and includes trenches that extend, starting from the front side, essentially perpendicularly into the drift region. First and second areas are situated between the trenches. The first areas are situated centrally between the trenches, and the second areas are situated between the first areas and the trenches. The first and second areas, starting from the body region, extend essentially perpendicularly into the drift region. The first areas include a third doping with the second charge carrier type, and the second areas include the first doping with the first charge carrier type.

公开(公告)号：US20240021610A1

公开(公告)日：2024-01-18

申请号：US18329550

申请日：2023-06-05

申请人： Robert Bosch GmbH

发明人： Josef Goeppert ,  Karl Oberdieck ,  Manuel Riefer ,  Neil Davies ,  Alexander Sewergin ,  Philipp Mueller

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7832 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/41766

摘要： A cascade arrangement and to a semiconductor module. The cascode arrangement includes: a substrate, a JFET, a MOSFET, and at least one sensor system. A drain terminal of the MOSFET is electrically connected to a source terminal of the JFET and a source terminal of the MOSFET is electrically connected to a gate terminal of the JFET. A first semiconductor layer in which the MOSFET is formed and a second semiconductor layer in which the JFET is formed, are situated stacked on top of one another via a connecting material. Both an electrical and a thermal coupling between the JFET and the MOSFET are implemented via the connecting material. The stacked semiconductor layers are situated on the substrate. The first semiconductor layer includes a first subarea in which the MOSFET is formed and at least one second subarea in which the at least one sensor system is formed.