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公开(公告)号：US08516199B2
公开(公告)日：2013-08-20
申请号：US12405483
申请日：2009-03-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F2212/1041
摘要： Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.
摘要翻译： 本发明的一些实施例提供了一种在支持基于目录的高速缓存相干方案的多处理器系统中处理对高速缓存行的请求的系统。 在操作期间，系统从家庭节点处的请求节点接收对高速缓存行的请求，其中家庭节点维护包括高速缓存行的地址空间的全部或子集的目录信息。 接下来，系统在家庭节点处执行动作，这导致高速缓存行的有效副本被发送到请求节点。 然后，系统在家庭节点处完成对请求的处理，而不等待指示请求节点接收到高速缓存行的有效副本的确认。
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公开(公告)号：US20100241814A1
公开(公告)日：2010-09-23
申请号：US12405483
申请日：2009-03-17
CPC分类号： G06F12/0817 , G06F2212/1041
摘要： Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.
摘要翻译： 本发明的一些实施例提供了一种在支持基于目录的高速缓存相干方案的多处理器系统中处理对高速缓存行的请求的系统。 在操作期间，系统从家庭节点处的请求节点接收对高速缓存行的请求，其中家庭节点维护包括高速缓存行的地址空间的全部或子集的目录信息。 接下来，系统在家庭节点处执行动作，这导致高速缓存行的有效副本被发送到请求节点。 然后，系统在家庭节点处完成对请求的处理，而不等待指示请求节点接收到高速缓存行的有效副本的确认。
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公开(公告)号：US07487327B1
公开(公告)日：2009-02-03
申请号：US11144117
申请日：2005-06-01
IPC分类号： G06F12/00
CPC分类号： G06F12/1475 , G06F12/1081
摘要： A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.
摘要翻译： 采用特定于设备的存储器地址转换的处理器。 在一个实施例中，处理器可以包括被配置为从输入/输出（I / O）设备接收存储器访问请求的设备接口，其中请求指定虚拟存储器地址和标识I的第一请求者标识符（ID） / O设备。 处理器还可以包括耦合到设备接口并被配置为确定对应于虚拟存储器地址的虚拟到物理存储器地址转换是否存储在I / O存储器转换缓冲器内的I / O存储器管理单元。 I / O存储器管理单元还可以被配置为确定存储在I / O存储器转换缓冲器内并对应于存储器地址转换的第二请求者ID是否匹配第一请求者ID。 如果第一和第二请求者ID不匹配，则I / O存储器管理单元可以不允许存储器访问请求并且发送错误状况。
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4.发明授权Memory controller and method using read and write queues and an ordering queue for dispatching read and write memory requests out of order to reduce memory latency 有权使用读写队列的内存控制器和方法以及排序读取和写入存储器请求的排序队列，以减少内存延迟公开(公告)号：US06877077B2
公开(公告)日：2005-04-05
申请号：US10020565
申请日：2001-12-07
申请人： Brian J. McGee , Jade B. Chau
发明人： Brian J. McGee , Jade B. Chau
CPC分类号： G06F13/1642
摘要： In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one write request in a write queue and queuing an incoming read request in a read queue. The method also includes comparing the read request with at least one write request in the write queue to detect a matching write request, and if there is a matching write request, storing a write queue index of the matching write request as a first entry in an ordering queue. The method further includes dispatching the at least one write request to the memory in response to the first ordering queue entry.
摘要翻译： 在本文公开的许多实施例中的一个实施例中，公开了一种用于向存储器发送读取和写入请求的方法，其包括在写入队列中排队至少一个写入请求并将读入队列中的传入读取请求排队。 该方法还包括将读取请求与写入队列中的至少一个写入请求进行比较以检测匹配的写入请求，并且如果存在匹配的写入请求，则将匹配的写入请求的写入队列索引作为第一条目存储在 订购队列。 所述方法还包括响应于所述第一排序队列条目向所述存储器分配所述至少一个写入请求。
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5.发明授权公开(公告)号：US06496917B1
公开(公告)日：2002-12-17
申请号：US09499264
申请日：2000-02-07
申请人： Rajasekhar Cherabuddi , Kevin B. Normoyle , Brian J. McGee , Meera Kasinathan , Anup Sharma , Sutikshan Bhutani
发明人： Rajasekhar Cherabuddi , Kevin B. Normoyle , Brian J. McGee , Meera Kasinathan , Anup Sharma , Sutikshan Bhutani
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F2212/2542 , G06F2212/507
摘要： A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative. If, on the other hand, the subsequent transaction requesting the specified data is a write transaction, the speculative request is canceled.
摘要翻译： 多处理器系统包括通过系统总线相互连接的多个中央处理单元（CPU）。 每个CPU包括与其高速缓存通信的高速缓存控制器以及与其主存储器通信的主存储器控制器。 当CPU中存在高速缓存未命中时，缓存控制器将主存储器的地址请求直接通过CPU作为推测请求直接发送到主存储器，而无需访问系统总线，并且还向系统总线发出地址请求以方便 数据一致性。 推测请求在主存储器控制器中排队，主存储器控制器又从指定的主存储器地址检索推测数据。 CPU监视系统总线以用于请求主存储器中指定数据的后续事务。 如果请求指定数据的后续事务是与推测地址请求相对应的读事务，则推测请求将被验证并变为非推测性。 另一方面，如果请求指定数据的后续事务是写事务，则推测请求被取消。
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