公开(公告)号：US4858173A

公开(公告)日：1989-08-15

申请号：US823775

申请日：1986-01-29

申请人： Robert E. Stewart ,  Paul J. Natusch ,  Eugene L. Yu ,  James B. Keller

发明人： Robert E. Stewart ,  Paul J. Natusch ,  Eugene L. Yu ,  James B. Keller

IPC分类号： G06F15/16 ,  G06F13/16 ,  G06F13/18 ,  G06F13/364 ,  G06F15/177

CPC分类号： G06F13/364

摘要： In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

摘要翻译： 在数据处理系统中，由仲裁单元确定由第一单元通过系统总线访问第二单元的数据处理系统，当接收对系统总线的访问的请求单元不能使用与第二单元交互的访问时 向仲裁单元和单元提供忙信号。 当子系统中止事务时，繁忙的信号导致单元重新建立访问系统总线的请求。 忙信号在系统总线的下一个仲裁中强制执行延迟，直到由于忙信号而导致中止事务的单元可以重新发送接入信号请求。 此外，可以在允许使用在原始仲裁时有效的优先级条件使总线访问总线的仲裁单元中包含设备。

公开(公告)号：US4954946A

公开(公告)日：1990-09-04

申请号：US453088

申请日：1989-12-21

申请人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1615

摘要： For use in a data processing system, a main memory subsystem includes a plurality of memory boards for storing groups of logic signals. Each memory board includes an plurality of array units. Each array unit is adapted to store a group of logic signals that is equivalent in size to the field of data logic signals transferred on the system bus and has an address structure so that each addressable data signal group can be stored in a single array. The address field of each array unit is further adapted so that the probability of interfering activity in each array is low. The arrays are adapted process data signal groups independently, thus, activity involving several arrays can take place simultaneously. The memory subsystem is structured to provide a pipeline types of overlapping activity so that activity involving several array units can be in progress simultaneously. Because the manipulation of the storage cells requires the most amounts of time in the memory unit, and because the arrays are performing this activity independently for each signal group, then the memory unit can be adapted to process the signal groups applied sequentially to the system without delay in nonexceptional circumstances, the most general exceptional circumstance being the masked write operation.

摘要翻译： 为了在数据处理系统中使用，主存储器子系统包括用于存储逻辑信号组的多个存储器板。 每个存储器板包括多个阵列单元。 每个阵列单元适于存储一组逻辑信号，其大小与在系统总线上传送的数据逻辑信号的字段相当，并且具有地址结构，使得每个可寻址数据信号组可以存储在单个阵列中。 每个阵列单元的地址字段进一步被适配，使得每个阵列中的干扰活动的概率很低。 阵列是独立的适应过程数据信号组，因此，可以同时进行涉及几个阵列的活动。 存储器子系统被构造为提供重叠活动的流水线类型，使得涉及若干阵列单元的活动可以同时进行。 由于存储单元的操作需要在存储器单元中大量的时间，并且由于阵列对于每个信号组独立地执行该活动，因此存储器单元可以适于处理顺序地施加到系统的信号组而无需 在非感知情况下的延迟，最常见的例外情况是屏蔽写操作。

公开(公告)号：US5168558A

公开(公告)日：1992-12-01

申请号：US495133

申请日：1990-03-19

申请人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia

发明人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia

IPC分类号： G06F13/16

CPC分类号： G06F13/1615

摘要： A main memory unit for a data processing system has at least one memory board and allows each memory board to process data simultaneously. Each memory board may also include a plurality of memory array units which also can process data simultaneously. The main memory unit includes a memory interface unit, at least one memory board, and a memory unit bus for transferring address, data, command, and memory status signals between the memory boards and the memory interface unit.

摘要翻译： 用于数据处理系统的主存储器单元具有至少一个存储器板，并允许每个存储器板同时处理数据。 每个存储器板还可以包括多个也可以同时处理数据的存储器阵列单元。 主存储器单元包括存储器接口单元，至少一个存储器板和用于在存储器板和存储器接口单元之间传送地址，数据，命令和存储器状态信号的存储器单元总线。

公开(公告)号：US4791552A

公开(公告)日：1988-12-13

申请号：US823951

申请日：1986-01-29

申请人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F12/06 ,  G11C8/18 ,  G06F12/00

CPC分类号： G06F12/0607 ,  G11C8/18

摘要： Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.

摘要翻译： 公开了用于选择要应用于存储器单元阵列的一组地址信号并将地址信号施加到存储器单元阵列以允许与地址信号相关联的活动完成的装置。 该装置产生控制锁存型缓冲存储单元的多个信号。 第一个产生的信号确保在将地址信号应用于系统总线时控制缓冲存储单元的信号有效。 第二产生的信号与第一生成信号重叠，并且将控制缓冲存储单元的信号扩展到少量。 第三产生的信号与第二个产生的信号重叠，并扩展控制缓冲存储单元的信号达到利用存储单元阵列所需的时间。

公开(公告)号：US4974153A

公开(公告)日：1990-11-27

申请号：US162620

申请日：1988-03-01

申请人： David W. Pimm ,  Paul J. Natusch ,  Robert T. Silver

发明人： David W. Pimm ,  Paul J. Natusch ,  Robert T. Silver

IPC分类号： G06F13/16 ,  G06F13/40

CPC分类号： G06F13/4036 ,  G06F13/1657

摘要： A system for implementing a repeater interlock scheme between a first and a second bus utilizes two repeaters. The first repeater coupled to the first bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second repeater which is coupled to memory through the second bus. The transaction buffer passes the interlock data for memory to the second bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the second bus.

摘要翻译： 用于在第一和第二总线之间实现中继器互锁方案的系统利用两个中继器。 耦合到第一总线的第一中继器包括在从处理器接受互锁事务时设置的互锁状态位。 互锁状态位置1时，不接受进一步的联锁交易。 互锁事务被传递到第二中继器中的事务缓冲器，其通过第二总线耦合到存储器。 事务缓冲器将存储器的互锁数据传递到第二总线，同时加载一个深度的互锁缓冲器。 从存储器返回到事务缓冲区的确认。 如果确认为联锁忙，则从联锁缓冲区重新进行联锁事务处理，从而允许事务缓冲区处理其他命令。 联锁缓冲器在重试互锁事务之前等待解锁写入信号，从而减轻第二总线上的拥塞。

公开(公告)号：US4897786A

公开(公告)日：1990-01-30

申请号：US93501

申请日：1987-09-04

申请人： David W. Pimm ,  Paul J. Natusch ,  Robert T. Silver

发明人： David W. Pimm ,  Paul J. Natusch ,  Robert T. Silver

IPC分类号： G06F13/16 ,  G06F13/40

CPC分类号： G06F13/1657 ,  G06F13/4036

摘要： A system for implementing a bus window interlock scheme between a first and a second bus utilizes two bus window modules. The first bus window module coupled to the processor bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second bus window module which is coupled to memory through the memory bus. The transaction buffer passes the interlock data for memory to the memory bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the memory bus.

摘要翻译： 用于在第一和第二总线之间实现总线窗口互锁方案的系统利用两个总线窗口模块。 耦合到处理器总线的第一总线窗口模块包括在从处理器接受互锁事务时被设置的联锁状态位。 互锁状态位置1时，不接受进一步的联锁交易。 互锁事务被传递到通过存储器总线耦合到存储器的第二总线窗口模块中的事务缓冲器。 事务缓冲区将存储器的互锁数据传递到存储器总线，同时加载一个深度的互锁缓冲器。 从存储器返回到事务缓冲区的确认。 如果确认为联锁忙，则从联锁缓冲区重新进行联锁事务处理，从而允许事务缓冲区处理其他命令。 联锁缓冲器在重试互锁事务之前等待解锁写入信号，从而减轻存储器总线上的拥塞。

公开(公告)号：US4809218A

公开(公告)日：1989-02-28

申请号：US823801

申请日：1986-01-29

申请人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr. deceased

发明人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr. deceased

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/36 ,  G06F12/02

CPC分类号： G06F13/28 ,  G06F13/16

摘要： In a data processing system having a multiple write command and a masked write command, a plurality of signal groups can be transferred from a data processing subsystem to a memory unit on consecutive system cycles. Associated with each signal group and applied to lines used to transfer mask signals are control signals that designate when the associated signal group is to stored in the memory unit. When the multiple write command is issued, the apparatus coupled to the mask signal lines is enabled and the control signals can be identified. When the control signals are identified, the operation storing the associated signal group is inhibited.

摘要翻译： 在具有多重写入命令和掩蔽写入命令的数据处理系统中，可以在连续的系统周期上将多个信号组从数据处理子系统传送到存储器单元。 与每个信号组相关并且应用于用于传送掩模信号的线路的控制信号是指定何时将相关信号组存储在存储器单元中的控制信号。 当发出多重写入命令时，启用耦合到掩模信号线的装置，并且可以识别控制信号。 当识别出控制信号时，禁止存储相关信号组的操作。