公开(公告)号：US20100011190A1

公开(公告)日：2010-01-14

申请号：US12170144

申请日：2008-07-09

申请人： Robert Golla ,  Manish Shah

发明人： Robert Golla ,  Manish Shah

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3851

摘要： A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

摘要翻译： 公开了能够解码与多个线程相关联的多个指令的微处理器。 微处理器可以包括第一阵列，其包括与来自多个内的指令相关联的第一多个微代码操作，第一阵列能够从第一多个微代码操作传送第一预定数量的微代码操作。 微处理器还可以包括包括第二多个微代码操作的第二阵列，所述第二阵列能够在所述指令解码成多于所述第一预定数量的微代码操作的情况下能够提供所述第二多个微代码操作中的一个或多个。 微处理器还可以包括耦合在第一和第二阵列之间的仲裁器，其中仲裁器可以确定来自多个线程的线程访问第二阵列。

公开(公告)号：US08195921B2

公开(公告)日：2012-06-05

申请号：US12170144

申请日：2008-07-09

申请人： Robert Golla ,  Manish Shah

发明人： Robert Golla ,  Manish Shah

IPC分类号： G06F15/00

CPC分类号： G06F9/3017 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3851

摘要： A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality of instructions, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

摘要翻译： 公开了能够解码与多个线程相关联的多个指令的微处理器。 微处理器可以包括第一阵列，其包括与来自多个指令内的指令相关联的第一多个微代码操作，第一阵列能够从第一多个微代码操作传送第一预定数量的微代码操作。 微处理器还可以包括包括第二多个微代码操作的第二阵列，所述第二阵列能够在所述指令解码成多于所述第一预定数量的微代码操作的情况下能够提供所述第二多个微代码操作中的一个或多个。 微处理器还可以包括耦合在第一和第二阵列之间的仲裁器，其中仲裁器可以确定来自多个线程的线程访问第二阵列。

公开(公告)号：US20060020831A1

公开(公告)日：2006-01-26

申请号：US10881092

申请日：2004-06-30

申请人： Robert Golla ,  Ricky Hetherington

发明人： Robert Golla ,  Ricky Hetherington

IPC分类号： G06F1/26

CPC分类号： G06F9/3869 ,  G06F1/32 ,  G06F1/3203 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3891

摘要： A method and apparatus for controlling power consumption in a processor. In one embodiment, a processor includes a pipeline. The pipeline includes logic for fetching instructions, issuing instructions, and executing instructions. The processor also includes a power management unit. The power management unit is configured to input M stalls into the pipeline every N instruction cycles (where M and N are integer value and wherein M is less than N).

摘要翻译： 一种用于控制处理器中的功率消耗的方法和装置。 在一个实施例中，处理器包括流水线。 流水线包括用于获取指令，发出指令和执行指令的逻辑。 处理器还包括电源管理单元。 电源管理单元被配置为每N个指令周期（其中M和N是整数值，并且其中M小于N）将M个时钟输入流水线。

公开(公告)号：US20060004995A1

公开(公告)日：2006-01-05

申请号：US10880488

申请日：2004-06-30

申请人： Ricky Hetherington ,  Gregory Grohoski ,  Robert Golla

发明人： Ricky Hetherington ,  Gregory Grohoski ,  Robert Golla

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/3885 ,  G06F12/0842 ,  G06F12/0859

摘要： An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of the plurality of thread groups may comprise a subset of the plurality of threads, to issue a first instruction from one of the plurality of threads during one execution cycle, and to issue a second instruction from another one of the plurality of threads during a successive execution cycle. The processor may further include a plurality of execution units, each configured to execute instructions issued from a respective thread group.

摘要翻译： 一种用于多行处理器核心中的细粒度多线程的装置和方法。 根据一个实施例，处理器可以包括指令提取逻辑，其被配置为将多个线程中的给定一个线程分配给多个线程组中的相应一个线程组，其中多个线程组中的每一个可以包括多个线程组的子集 线程，以在一个执行周期期间从多个线程之一发出第一指令，并且在连续执行周期期间从多个线程中的另一个发出第二指令。 处理器还可以包括多个执行单元，每个执行单元被配置为执行从相应的线程组发出的指令。

公开(公告)号：US20060005051A1

公开(公告)日：2006-01-05

申请号：US10881246

申请日：2004-06-30

申请人： Robert Golla ,  Jeffrey Brooks ,  Christopher Olson

发明人： Robert Golla ,  Jeffrey Brooks ,  Christopher Olson

IPC分类号： G06F1/26

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3851 ,  Y02D10/128 ,  Y02D10/171

摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.

公开(公告)号：US20060004989A1

公开(公告)日：2006-01-05

申请号：US10881247

申请日：2004-06-30

申请人： Robert Golla

发明人： Robert Golla

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/3861

摘要： In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given cycle, a valid instruction based upon a thread selection algorithm. The pick unit may further cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.

摘要翻译： 在一个实施例中，多线程处理器包括多个缓冲器，每个缓冲器被配置为存储对应于相应线程的指令。 多线程处理器还包括耦合到多个缓冲器的拾取单元。 拾取单元可以在给定周期中从至少一个缓冲器中选择基于线程选择算法的有效指令。 拾取单元可以在给定的周期中进一步取消响应于接收到取消指示而选择有效指令。