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1.发明授权Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer 失效用于通过中间缓冲器控制从生产者到缓冲消费者的高频数字系统中的信息流的方法和系统公开(公告)号：US06598086B1
公开(公告)日：2003-07-22
申请号：US09436961
申请日：1999-11-09
IPC分类号： G06F1516
CPC分类号： H04L47/527 , H04L47/28 , H04L47/50 , H04L49/90
摘要： An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.
摘要翻译： 信息处理系统包括多个依次连接的单元，包括第一单元，第二单元和第三单元。 信息包从第一单元直接传输到第二单元，然后流向第三单元，并且多个单元中的每个单元提供指示该单元是否输出分组的相应的动态输出指示。 所述信息处理系统还包括：控制单元，其确定利用所述多个动态输出指示中的所有多个单元的分组缓冲能力以及所述多个单元中的相邻单元之间的保证的分组流，如果所述第一单元可以输出 一个数据包直接连到第二个单元没有丢包。 响应于该确定，控制单元向第一单元输出控制信号。
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2.发明授权Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path 失效用于通过中间缓冲器和共享数据路径来控制从生产者到缓冲用户的高频数字系统中的信息流的方法和系统公开(公告)号：US06604145B1
公开(公告)日：2003-08-05
申请号：US09436963
申请日：1999-11-09
IPC分类号： G06F1516
摘要： An information handling system includes a plurality of producers that output packets of information, at least one consumer of the packets, and an information pipeline coupling the consumer and at least a particular producer among the plurality of producers. The information pipeline includes a shared resource having a bandwidth shared by multiple of the plurality of producers. The information handling system further includes a control unit that regulates packet output of the particular producer and that receives as inputs a producer output indication indicating that the particular producer output a packet and a shared resource input indication indicating that a packet output by the particular producer has been accepted by the shared resource for transmission to the consumer. Based upon these inputs, a number of grant messages output to the particular producer within a feedback latency of the control unit, and a portion of the bandwidth allocated to the particular producer, the control unit whether the particular producer can output a packet without packet loss. In response to a determination that the particular producer can output a packet without packet loss, the control unit outputs a grant message to the particular producer indicating that the particular producer is permitted to output a packet.
摘要翻译： 信息处理系统包括输出信息分组的多个生成器，分组的至少一个消费者，以及耦合消费者和多个生产者中的至少特定生产者的信息流水线。 信息流水线包括具有由多个生产者中的多个共享的带宽的共享资源。 信息处理系统还包括控制单元，其调节特定生产者的分组输出并且接收指示特定生成者输出分组的生成器输出指示和指示由特定生产者输出的分组的共享资源输入指示 由共享资源接受传输给消费者。 基于这些输入，在控制单元的反馈等待时间内向特定生产者输出的许多授权消息以及分配给特定生产者的带宽的一部分，控制单元特定生产者是否可以输出分组而不丢包 。 响应于确定特定制作者可以输出没有分组丢失的分组，控制单元向特定制作者输出指示特定制作者被允许输出分组的授权消息。
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3.发明授权Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system 有权用于控制高频数字系统中的生产者和多个缓冲器之间的信息流的方法和系统公开(公告)号：US06601105B1
公开(公告)日：2003-07-29
申请号：US09436960
申请日：1999-11-09
IPC分类号： G06F1516
CPC分类号： G06F15/17
摘要： An information handling system includes a producer that outputs packets of information, a plurality of buffers that can each receive packets from the producer and output the packets, and a control unit. The control unit receives at least one producer output indication indicating whether the producer output a packet to one of the plurality of buffers and a plurality of buffer output indications that each indicate whether a respective one of the plurality of buffers has output a packet. Based upon capacities of the plurality of buffers, the producer output indications, the buffer output indications and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. If so, the control unit provides a grant message to the producer indicating that the producer is permitted to output a packet.
摘要翻译： 信息处理系统包括输出信息包的生成器，可以从生产者接收分组并输出分组的多个缓冲器，以及控制单元。 所述控制单元接收至少一个生成器输出指示，所述至少一个生成器输出指示指示所述生成器是否向多个缓冲器之一输出分组，以及多个缓冲器输出指示，每个指示所述多个缓冲器中的相应一个是否已经输出分组。 基于多个缓冲器的能力，生成器输出指示，缓冲器输出指示和在控制单元的反馈等待时间内向生成器输出的许多准许消息，控制单元是否可以输出分组而不丢包 。 如果是，则控制单元向生产者提供指示允许生产者输出分组的授权消息。
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4.发明授权Method and system for controlling information flow between a producer and a buffer in a high frequency digital system 失效用于控制高频数字系统中的制造商和缓冲器之间的信息流的方法和系统公开(公告)号：US06606666B1
公开(公告)日：2003-08-12
申请号：US09436962
申请日：1999-11-09
IPC分类号： G06F1516
摘要： An information handling system includes a producer that outputs packets, a buffer that receives packets from the producer, buffers the packets, and eventually outputs the packets, and a control unit that controls the flow of packets from the producer to the buffer. The control unit receives as inputs a producer output indication indicating that the producer has output a packet to the buffer and a buffer output indication indicating that the buffer has output a packet. Based upon a capacity of the buffer, a number of the producer output indications, a number of buffer output indications, and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. In response to a determination that the producer can output a packet without packet loss, the control unit outputs a grant message to the producer indicating that the producer is permitted to output a packet.
摘要翻译： 信息处理系统包括输出分组的生成器，从生成器接收分组的缓冲器，缓冲分组，最终输出分组，以及控制单元，控制从生成器到缓冲器的分组流。 控制单元作为输入接收指示生成者已经向缓冲器输出分组的生成器输出指示和指示缓冲器已经输出分组的缓冲器输出指示。 基于缓冲器的容量，多个生成器输出指示，多个缓冲器输出指示以及在控制单元的反馈等待时间内向生成器输出的许多准许消息，控制单元是否可以输出 一个没有数据包丢失的数据包。 响应于确定生产者可以输出没有分组丢失的分组，控制单元向生产者输出授权消息，指示生产者被允许输出分组。
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公开(公告)号：US20100268882A1
公开(公告)日：2010-10-21
申请号：US12424207
申请日：2009-04-15
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Stephen James Powell , William John Starke , Jeffrey A. Stuecheli
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Stephen James Powell , William John Starke , Jeffrey A. Stuecheli
CPC分类号： G06F12/123 , G06F12/084 , G06F12/0897
摘要： A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.
摘要翻译： 用于跟踪核心负载请求并提供仲裁和请求排序的系统和方法。 当核心接口单元（CIU）从处理器核心接收到加载操作时，分配在CIU队列中的新条目。 响应于在队列中分配新条目，CIU检测加载请求和另一个存储器访问请求之间的争用。 响应于检测到争用，负载请求可以被暂停，直到争用被解决。 接收到的加载请求可以存储在队列中，并使用最近最少使用的（LRU）机制进行跟踪。 然后可以在加载请求驻留在加载请求队列中最近最少使用的条目中时处理加载请求。 除非读取权利要求（RC）机器可用，否则CIU也可以暂停发出指令。 在另一个实施例中，CIU可以以特定优先级顺序发布存储的加载请求。
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6.发明授权Data processing system providing hardware acceleration of input/output (I/O) communication 有权数据处理系统提供输入/输出（I / O）通讯的硬件加速公开(公告)号：US07047320B2
公开(公告)日：2006-05-16
申请号：US10339724
申请日：2003-01-09
IPC分类号： G06F3/00
CPC分类号： G06F13/124 , G06F12/0835
摘要： An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.
摘要翻译： 诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。 集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合 通过输入/输出通信链路支持输入/输出通信的处理器核心。
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7.发明授权Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism 有权在ECC保护机制中应用特殊ECC矩阵解决卡位故障公开(公告)号：US07069494B2
公开(公告)日：2006-06-27
申请号：US10418549
申请日：2003-04-17
IPC分类号： H03M13/11
CPC分类号： G06F11/1064 , H03M13/13
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted. Thereafter, the data is re-read from the array, and if the error was due to a hard fault (stuck bit), it will appear correct (after applying the polarity indicated by the inversion bit), since the inversion will have changed the value of the defective bit to the stuck value. The inversion bit may be part of the data itself. In this case, one of the columns in the ECC matrix corresponds to the inversion bit, and each bit in that column of the matrix is set. In the case of an ECC protected mechanism such as a system bus, once a stuck bit condition is detected, the sending device can elect to send data such that the polarity of the data for that bit is always flipped to match the logic level of the stuck value on the wire. This approach allows for full single-bit correct, double-bit detect even in the presence of a stuck bit.
摘要翻译： 一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位 纠错和（N-1）位错误检测。 在说明性实施例中，ECC矩阵在其每行中设置奇数位。 在诸如存储器件的ECC保护机制的情况下，这些属性有利于使用反转位来校正所存储的数据中的硬故障。 当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。 因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。 此后，数据从阵列重新读取，如果错误是由于硬故障（卡位）引起的，则会显示正确的（应用反转位指示的极性后），因为反转将会改变 有缺陷位的值到卡住值。 反转位可能是数据本身的一部分。 在这种情况下，ECC矩阵中的列之一对应于反转比特，矩阵的该列中的每个比特被设置。 在诸如系统总线的ECC保护机制的情况下，一旦检测到卡位状态，发送设备就可以选择发送数据，使得该位的数据的极性总是被翻转以匹配 在线上卡住了值。 这种方法允许完全单位正确，双位检测，即使存在卡位。
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8.发明授权Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems 失效稳定的系统可靠性通过收缩制造级芯片测试在微处理器/系统上的实时操作公开(公告)号：US07039832B2
公开(公告)日：2006-05-02
申请号：US10313329
申请日：2002-12-05
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.
摘要翻译： 公开了一种方法和系统，用于通过中断非测试过程的处理器执行来在安装的处理器上运行制造级测试程序。 制造级测试程序的定期执行允许处理器在正常功能操作期间不间断地进行自检，以便促进处理器和处理器作为其一部分的数据处理系统的适当维护和功能。
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9.发明授权Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制公开(公告)号：US07849298B2
公开(公告)日：2010-12-07
申请号：US12352462
申请日：2009-01-12
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。
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公开(公告)号：US07272664B2
公开(公告)日：2007-09-18
申请号：US10313330
申请日：2002-12-05
IPC分类号： G06F15/16 , G06F15/167 , G06F15/00 , G06F15/76
CPC分类号： G06F9/4812 , G06F9/30116 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.
摘要翻译： 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器访问数据处理系统中的任何处理器，用于将处理器的处理状态存储到存储器中，而与处理器上运行的操作系统无关。
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