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1.发明授权Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs 失效最小布局扰动为基础的艺术品合法化与层次设计的网格约束公开(公告)号：US07484197B2
公开(公告)日：2009-01-27
申请号：US11279758
申请日：2006-04-14
申请人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译： 一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。 该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置 使用线性规划解决方案的结果的至少一个小区。
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2.发明授权公开(公告)号：US07761821B2
公开(公告)日：2010-07-20
申请号：US11837732
申请日：2007-08-13
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。
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3.发明授权公开(公告)号：US07302651B2
公开(公告)日：2007-11-27
申请号：US10904225
申请日：2004-10-29
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。
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4.发明授权公开(公告)号：US07257783B2
公开(公告)日：2007-08-14
申请号：US10905008
申请日：2004-12-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移 具有较差的基本规则。
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5.发明授权公开(公告)号：US08464189B2
公开(公告)日：2013-06-11
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。
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6.发明申请TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效用于具有放射性设计限制的集成电路的技术移动公开(公告)号：US20100185997A1
公开(公告)日：2010-07-22
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。
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7.发明授权公开(公告)号：US07610565B2
公开(公告)日：2009-10-27
申请号：US11697798
申请日：2007-04-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移 具有较差的基本规则。
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8.发明申请METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译： 一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。
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9.发明授权Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译： 一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。
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公开(公告)号：US07260790B2
公开(公告)日：2007-08-21
申请号：US10709292
申请日：2004-04-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.
摘要翻译： 一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。
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