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    Reduced area of crossbar and method of operation
    1.
    发明授权
    Reduced area of crossbar and method of operation 失效
    横梁面积减小和作业方式

    公开(公告)号：US5768609A

    公开(公告)日：1998-06-16

    申请号：US483657

    申请日：1995-06-07

    申请人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    发明人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    IPC分类号： G06F15/173 ,  G06F15/80

    CPC分类号： G06F15/17375

    摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

    摘要翻译： 已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。 图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。 交叉开关用于建立处理器存储器链路。 整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

    Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware
    2.
    发明授权
    Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware 失效
    单一集成电路体现了具有单独指令处理硬件的双异质处理器

    公开(公告)号：US06948050B1

    公开(公告)日：2005-09-20

    申请号：US09875136

    申请日：2001-06-06

    申请人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    发明人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    IPC分类号： G06F9/38 ,  G06F15/16 ,  G06F15/173

    CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F15/17375

    摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

    摘要翻译： 单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。 单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。 两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。

    Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor
    3.
    发明授权
    Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
    具有多个具有与每个处理器对应的统一地址空间的存储器的多处理系统中的唯一处理器标识符

    公开(公告)号：US5696913A

    公开(公告)日：1997-12-09

    申请号：US472827

    申请日：1995-06-07

    申请人： Robert J. Gove ,  Karl Marion Guttag ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons

    发明人： Robert J. Gove ,  Karl Marion Guttag ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons

    IPC分类号： G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F15/17375 ,  G06F12/0284

    摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.

    摘要翻译： 多处理系统包括多个存储器和多个处理器。 每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。 每个处理器具有预定的多个对应的存储器。 这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。 连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。 每个处理器具有一个具有唯一地识别多处理系统内的处理器的多个只读位的寄存器。 处理器可以采用这种唯一的处理器标识符来计算对应于该处理器的基地址。 这使得能够独立于多处理系统内的处理器执行的程序。

    Single integrated circuit embodying a risc processor and a digital signal processor
    4.
    发明授权
    Single integrated circuit embodying a risc processor and a digital signal processor 失效
    单个集成电路体现了一个risc处理器和一个数字信号处理器

    公开(公告)号：US06260088B1

    公开(公告)日：2001-07-10

    申请号：US09517990

    申请日：2000-03-03

    申请人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    发明人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    IPC分类号： G06F1300

    CPC分类号： G06F15/17375

    摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

    摘要翻译： 单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。 单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。 两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。

    System and method of memory access in apparatus having plural processors and plural memories
    5.
    发明授权
    System and method of memory access in apparatus having plural processors and plural memories 失效
    具有多个处理器和多个存储器的设备中的存储器访问的系统和方法

    公开(公告)号：US6070003A

    公开(公告)日：2000-05-30

    申请号：US264582

    申请日：1994-06-22

    申请人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    发明人： Robert J. Gove ,  Keith Balmer ,  Nicholas Kerin Ing-Simmons ,  Karl Marion Guttag

    IPC分类号： G06F15/173 ,  G06F13/16

    CPC分类号： G06F15/17375

    摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

    摘要翻译： 已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。 图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。 交叉开关用于建立处理器存储器链路。 整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。