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1.发明授权公开(公告)号：US06366518B1
公开(公告)日：2002-04-02
申请号：US09571486
申请日：2000-05-15
IPC分类号： G11C700
CPC分类号： G11C17/18
摘要： A circuit includes a programmable element having conductor track resistance that can be permanently altered by an electric current. The circuit also has a switchable element for receiving a control signal for programming the programmable element. The programmable element and the switchable element are connected in series between two supply potentials. The programmable element can have an electrical fuse. The input of a read-out circuit is connected through a protective circuit to the circuit node between the programmable element and the switchable element. The protective circuit serves for limiting the voltage potential at the input of the read-out circuit during a programming operation. The circuit elements of the read-out circuit can thus be dimensioned in an area-saving manner. The protective circuit also can include a diode having an anode connected to the input of the read-out circuit and a cathode connected to a third supply potential. The protective circuit can include resistors, one disposed between the anode and input of the read-out circuit and another disposed between the anode and the circuit node.
摘要翻译： 电路包括具有能够被电流永久改变的导体轨道电阻的可编程元件。 电路还具有用于接收用于编程可编程元件的控制信号的可切换元件。 可编程元件和可切换元件串联连接在两个电源之间。 可编程元件可以具有电熔丝。 读出电路的输入通过保护电路连接到可编程元件和可切换元件之间的电路节点。 保护电路用于在编程操作期间限制读出电路输入端的电压电位。 因此，读出电路的电路元件可以以面积节省的方式设计。 保护电路还可以包括具有连接到读出电路的输入端的阳极和连接到第三电源电位的阴极的二极管。 保护电路可以包括电阻器，一个设置在读出电路的阳极和输入端之间，另一个设置在阳极和电路节点之间。
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公开(公告)号：US06178124B1
公开(公告)日：2001-01-23
申请号：US09401388
申请日：1999-09-22
IPC分类号： G11C700
CPC分类号： G11C29/835
摘要： The integrated memory has memory cells which are combined to form individually addressable standard units, and one or more redundant units for replacing one of the standard units on an address basis. The memory also has a self-test unit for performing a function test on the memory cells and for performing an analysis as to which of the standard units is to be replaced by a respective redundant unit. There is also a first memory unit for storing the address, determined by the self-test unit, of the standard unit which is to be replaced by the redundant unit, and a comparison unit connected to an address bus and to outputs of the first memory unit, for comparing an address present on the address bus with the address stored in the first memory unit. The comparison unit activates the redundant unit if a match is recognized. The first memory unit has at least one output which is connected to a corresponding output of the integrated circuit for outputting the respectively stored address.
摘要翻译： 集成存储器具有被组合以形成单独可寻址标准单元的存储单元，以及一个或多个冗余单元，用于以地址为基础替换标准单元之一。 存储器还具有用于对存储器单元执行功能测试并且用于执行关于哪个标准单元将被相应的冗余单元替换的分析的自检单元。 还存在用于存储由自检单元确定的由冗余单元替代的标准单元的地址的第一存储单元，以及连接到地址总线的比较单元和第一存储器的输出 单元，用于将地址总线上存在的地址与存储在第一存储器单元中的地址进行比较。 如果识别出匹配，比较单元激活冗余单元。 第一存储单元具有连接到集成电路的相应输出的至少一个输出，用于输出分别存储的地址。
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公开(公告)号：US06800817B2
公开(公告)日：2004-10-05
申请号：US10055522
申请日：2002-01-23
IPC分类号： G01R3128
CPC分类号： G11C29/48
摘要： The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor component at a connection provided for that purpose on the semiconductor component. The latter has a clock recovery circuit, which obtains a periodic clock signal from the modulated clock signal, and a shift register, to which the modulated clock signal can be fed in a manner clocked by the periodic clock signal and which provides a data signal. The present invention makes it possible, in particular in mass memory chips, to feed in clock signals and also program, address or data signals for the realization of BIST via just one connection contact.
摘要翻译： 提供半导体元件用于连接到测试系统。 具有调制占空比的外部时钟信号可以在半导体部件上为此设置的连接处输入到半导体部件。 后者具有从调制时钟信号获得周期性时钟信号的时钟恢复电路和移位寄存器，调制时钟信号可以以周期性时钟信号所提供的方式馈送到该移位寄存器，并提供数据信号。 本发明使得特别是在大容量存储器芯片中，通过仅一个连接接点，可以馈送时钟信号以及用于实现BIST的程序，地址或数据信号。
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4.发明授权Configuration for generating signal impulses of defined lengths in a module with a bist-function 有权用于在具有双功能的模块中产生定义长度的信号脉冲的配置公开(公告)号：US06715118B2
公开(公告)日：2004-03-30
申请号：US09781208
申请日：2001-02-12
IPC分类号： G01R31317
CPC分类号： G01R31/31858 , H03K5/131 , H03K5/133
摘要： In the configuration, the module can “learn” one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.
摘要翻译： 在配置中，模块可以从外部测试器“学习”一个或多个时间间隔，然后在内部重复，或将其与其自身内部测量的时间间隔进行比较，例如，为了评估所讨论的模块是否已经越过 时间规格值或低于该值。 该模块还可以测量和存储一个或多个内部时间间隔，并以数字或模拟形式将其传输到外部测试仪。
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公开(公告)号：US06449206B2
公开(公告)日：2002-09-10
申请号：US09867292
申请日：2001-05-29
IPC分类号： G11C800
CPC分类号： G11C17/18
摘要： In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.
摘要翻译： 为了编程可编程元件，提出以半导体电路配置将可编程元件的第一和第二连接端子连接到设置在半导体电路配置中的第一和/或第二电位器件。 以这种方式，第一和第二电位本质上可用于形成用于编程可编程元件的燃烧电压。
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公开(公告)号：US06804166B2
公开(公告)日：2004-10-12
申请号：US10680773
申请日：2003-10-07
IPC分类号： G11C800
CPC分类号： G11C7/1012 , G11C7/1072 , G11C7/22
摘要： A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.
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公开(公告)号：US06535046B2
公开(公告)日：2003-03-18
申请号：US10187759
申请日：2002-07-02
IPC分类号： H03L500
CPC分类号： H01L27/088
摘要： An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.
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公开(公告)号：US06441677B1
公开(公告)日：2002-08-27
申请号：US09621430
申请日：2000-07-21
IPC分类号： H03K110
CPC分类号： H01L27/088
摘要： An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.
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9.发明授权Method for determining the drive capability of a driver circuit of an integrated circuit 有权用于确定集成电路的驱动电路的驱动能力的方法公开(公告)号：US06320368B1
公开(公告)日：2001-11-20
申请号：US09401387
申请日：1999-09-22
IPC分类号： G01R3128
CPC分类号： G01R31/2836
摘要： A method provides that, when a driver circuit is deactivated, a first capacitor disposed at an output of the driver circuit is placed at a first potential. The driver circuit is then activated at a first point in time, so that a current flows between its output and the first capacitor. The flow of current between the output of the driver circuit and the first capacitor is interrupted at a second point in time and the potential at the first capacitor is subsequently determined as a measure of the drive capability of the driver circuit.
摘要翻译： 一种方法规定，当驱动器电路被去激活时，设置在驱动器电路的输出处的第一电容器被置于第一电位。 然后，驱动器电路在第一时间点被激活，使得电流在其输出和第一电容器之间流动。 驱动电路的输出与第一电容器之间的电流在第二时间点被中断，并且随后确定第一电容器处的电位作为驱动电路的驱动能力的量度。
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10.发明授权Integrated circuit having a programmable element and method of operating the circuit 失效具有可编程元件的集成电路和操作该电路的方法公开(公告)号：US06788129B2
公开(公告)日：2004-09-07
申请号：US10301090
申请日：2002-11-20
IPC分类号： H01H3776
CPC分类号： G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.
摘要翻译： 集成电路具有可通过编程改变的电互连电阻的可编程元件。 用于评估电互连电阻的评估电路连接到可编程元件。 可编程元件的电互连电阻由评估电路读出和评估。 利用与评估电路连接的微调电路，根据由评估电路读出的电互连电阻来调节评估电路的工作点。 以这种方式，可以独立于技术波动来读出和评估可编程元件的状态。
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