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    METHOD AND APPARATUS FOR EFFICIENT MATRIX ALIGNMENT IN A SYSTOLIC ARRAY
    4.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENT MATRIX ALIGNMENT IN A SYSTOLIC ARRAY 审中-公开

    公开(公告)号：US20190042262A1

    公开(公告)日：2019-02-07

    申请号：US16147506

    申请日：2018-09-28

    申请人： Michael Espig ,  Bret Toll ,  Raanan Sade ,  Robert Valentine ,  Alexander Heinecke

    发明人： Michael Espig ,  Bret Toll ,  Raanan Sade ,  Robert Valentine ,  Alexander Heinecke

    IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F9/30

    摘要： An apparatus and method for efficient matrix alignment in a systolic array. For example, one embodiment of a processor comprises: a first set of physical tile registers to store first matrix data in rows or columns; a second set of physical tile registers to store second matrix data in rows or columns; a decoder to decode a matrix instruction identifying a first input matrix, a first offset, a second input matrix, and a second offset; and execution circuitry, responsive to the matrix instruction, to read a subset of rows or columns from the first set of physical tile registers in accordance with the first offset, spanning multiple physical tile registers from the first set if indicated by the first offset to generate a first input matrix and the execution circuitry to read a subset of rows or columns from the second set of physical tile registers in accordance with the second offset, spanning multiple physical tile registers from the second set if indicated by the second offset to generate a second input matrix; and the execution circuitry to perform an arithmetic operation with the first and second input matrices in accordance with an opcode of the matrix instruction.

    FLOATING POINT ROUNDING PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    5.
    发明申请
    FLOATING POINT ROUNDING PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    浮点处理器，方法，系统和指令

    公开(公告)号：US20130290685A1

    公开(公告)日：2013-10-31

    申请号：US13976792

    申请日：2011-12-22

    申请人： Jesus Corbal San Adrian ,  Cristina S. Anderson ,  Robert Valentine ,  Bret Toll ,  Amit Gradstein ,  Simon Rubanovich ,  Benny Eitan

    发明人： Jesus Corbal San Adrian ,  Cristina S. Anderson ,  Robert Valentine ,  Bret Toll ,  Amit Gradstein ,  Simon Rubanovich ,  Benny Eitan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/30014 ,  G06F9/30036

    摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译： 一方面的方法包括接收浮点舍入指令。 浮点舍入指令指示一个或多个浮点数据元素的源，指示在一个或多个浮点数据元素中的每一个要四舍五入的基数点之后的分数比特的数量，并且指示目的地存储位置 。 响应于浮点舍入指令，结果存储在目的地存储位置。 结果包括一个或多个舍入结果浮点数据元素。 一个或多个圆化结果浮点数据元素中的每一个包括源的浮点数据元素中的一个，在对应位置中，其被舍入到所指示的小数位数。 公开了其它方法，装置，系统和指令。

    Method and apparatus for disabling a clock signal within a multithreaded processor
    8.
    发明授权
    Method and apparatus for disabling a clock signal within a multithreaded processor 有权
    用于在多线程处理器内禁用时钟信号的方法和装置

    公开(公告)号：US06883107B2

    公开(公告)日：2005-04-19

    申请号：US10095357

    申请日：2002-03-08

    申请人： Dion Rodgers ,  Bret Toll ,  Aimee Wood

    发明人： Dion Rodgers ,  Bret Toll ,  Aimee Wood

    IPC分类号： G06F15/00 ,  G06F9/38 ,  G06F1/08 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/384 ,  G06F9/3851 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

    摘要： A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

    摘要翻译： 一种方法包括相对于在多线程处理器中支持的多个线程中的每一个来维护待决事件的指示。 对于多个线程中的每一个，还保持指示为活动状态或非活动状态。 检测到时钟禁止条件。 该时钟禁用条件可以由相对于多个线程中的每个线程的不存在的事件以及针对多个线程中的每一个的不活动状态来指示。 响应于检测到时钟禁止条件，相对于多线程处理器内的至少一个功能单元，如果允许时钟信号被禁用。