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1.发明申请SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER 失效用于执行可编程DMA主机的系统和方法，日期检查使用DRONE系统控制器公开(公告)号：US20080312863A1
公开(公告)日：2008-12-18
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译： 一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。 根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。 无人机处理器将随机数据集合的第三副本写入处理器存储器。 当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。 当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。
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2.发明授权Implementing a programmable DMA master with write inconsistency determination 失效实现具有写入不一致性确定的可编程DMA主机公开(公告)号：US08165847B2
公开(公告)日：2012-04-24
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译： 一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。 根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。 无人机处理器将随机数据集合的第三副本写入处理器存储器。 当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。 当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。
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3.发明授权System and method for implementing a programmable DMA master with data checking utilizing a drone system controller 失效使用无人机系统控制器实现具有数据检查的可编程DMA主机的系统和方法公开(公告)号：US07430487B2
公开(公告)日：2008-09-30
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译： 一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。 根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。 无人机处理器将随机数据集合的第三副本写入处理器存储器。 当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。 当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。
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4.发明申请System and Method for Implementing a Programmable DMA Master With Date Checking Utilizing a Drone System Controller 失效使用无人机系统控制器实现可编程DMA主机的日期检查的系统和方法公开(公告)号：US20080059103A1
公开(公告)日：2008-03-06
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译： 一种方法，系统和计算机可用介质，用于使用无人机系统控制器实现具有日期检查的可编程DMA主机。 根据本发明的优选实施例，无人机处理器生成随机数据的集合，并将随机数据集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。 无人机处理器将随机数据集合的第三副本写入处理器存储器。 当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。 当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。
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公开(公告)号：US07953510B2
公开(公告)日：2011-05-31
申请号：US11855000
申请日：2007-09-13
IPC分类号： G06F19/00
CPC分类号： H01L23/544 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.
摘要翻译： 提出了一种用于半导体识别芯片读出的系统和方法。 用户使用独立的手持设备从半导体器件提取包括制造工艺属性的产品数据。 半导体器件通过诸如电源引脚，接地引脚，引脚时钟和数据输出引脚的引脚子集耦合到手持设备。 当耦合时，手持设备向半导体器件提供时钟信号。 反过来，半导体器件内的片上逻辑检测时钟信号并收集内部产品数据。 一旦收集，片上逻辑通过数据输出引脚向手持设备提供产品数据，供用户查看。 结果，用户可以更有效地跟踪半导体器件。
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公开(公告)号：US20090076641A1
公开(公告)日：2009-03-19
申请号：US11855000
申请日：2007-09-13
IPC分类号： G06F19/00
CPC分类号： H01L23/544 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.
摘要翻译： 提出了一种用于半导体识别芯片读出的系统和方法。 用户使用独立的手持设备从半导体器件提取包括制造工艺属性的产品数据。 半导体器件通过诸如电源引脚，接地引脚，引脚时钟和数据输出引脚的引脚子集耦合到手持设备。 当耦合时，手持设备向半导体器件提供时钟信号。 反过来，半导体器件内的片上逻辑检测时钟信号并收集内部产品数据。 一旦收集，片上逻辑通过数据输出引脚将产品数据提供给手持设备，供用户查看。 结果，用户可以更有效地跟踪半导体器件。
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7.发明授权Method and apparatus for power throttling a processor in an information handling system 有权用于在信息处理系统中对处理器进行功率调节的方法和装置公开(公告)号：US07793125B2
公开(公告)日：2010-09-07
申请号：US11621710
申请日：2007-01-10
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/266 , G06F1/329 , G06F1/3296 , G06F9/3836 , G06F9/3869 , G06F9/3891 , Y02D10/172 , Y02D10/24 , Y02D50/20
摘要： A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.
摘要翻译： 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率超过预定阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速率，以提供功率节流。 与期望的输出电压相比，电力系统动态响应处理器电路从电力系统接收的实际输出电压的变化，并对这种变化进行校正。
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8.发明申请Method and Apparatus for Power Throttling a Processor in an Information Handling System 有权用于在信息处理系统中调节处理器的功率的方法和装置公开(公告)号：US20080168287A1
公开(公告)日：2008-07-10
申请号：US11621710
申请日：2007-01-10
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/266 , G06F1/329 , G06F1/3296 , G06F9/3836 , G06F9/3869 , G06F9/3891 , Y02D10/172 , Y02D10/24 , Y02D50/20
摘要： A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.
摘要翻译： 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率超过预定阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速率，以提供功率节流。 与期望的输出电压相比，电力系统动态响应处理器电路从电力系统接收的实际输出电压的变化，并对这种变化进行校正。
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