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公开(公告)号：US07471098B2
公开(公告)日：2008-12-30
申请号：US10975663
申请日：2004-10-28
IPC分类号： G01R31/02
CPC分类号： G01R31/31723 , G01R31/2884 , G01R31/31703
摘要： An apparatus and method are provided for testing integrated circuits. An integrated circuit arrangement is provided having first and second dice. Each die has circuitry for diagnostic testing in response to a diagnostic test signal. The circuitry further defines an input for receiving the diagnostic test signal and an output for transmitting results of the diagnostic testing for each of the dice. Interconnecting circuitry between the dice transmits the diagnostic test signal transmitted to the first die to the second die before the diagnostic testing is completed in the first die.
摘要翻译： 提供了一种用于测试集成电路的装置和方法。 提供具有第一和第二骰子的集成电路装置。 每个管芯具有用于响应于诊断测试信号进行诊断测试的电路。 该电路进一步限定用于接收诊断测试信号的输入端和用于传送针对每个骰子的诊断测试结果的输出。 在诊断测试在第一个模具中完成之前，骰子之间的互连电路将传输到第一裸片的诊断测试信号发送到第二个裸片。
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公开(公告)号：US08024490B2
公开(公告)日：2011-09-20
申请号：US10767505
申请日：2004-01-28
IPC分类号： G06F3/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0659 , G06F3/0674
摘要： According to one embodiment of the present invention, a data storage device comprises a generic host interface and a media controller. The host interface has a channel select bit encoder to assert one or more channel select bits to be decoded by the media controller to indicate one or more virtual channels through which the host interface will communicate with the media controller over a data bus. A virtual channel controller in the host interface establishes a peer-to-peer connection with a virtual channel controller in the media controller based on the virtual channel indicated by the one or more channel select bits. A communication controller in the host interface implements a communication protocol for communication with a host and transfers data to and from the media controller via the peer-to-peer connection based on the communication with the host.
摘要翻译： 根据本发明的一个实施例，数据存储设备包括通用主机接口和媒体控制器。 主机接口具有信道选择位编码器，用于断言由媒体控制器解码的一个或多个信道选择位，以指示主机接口将通过数据总线与媒体控制器通信的一个或多个虚拟信道。 主机接口中的虚拟通道控制器基于由一个或多个通道选择位指示的虚拟通道建立与媒体控制器中的虚拟通道控制器的对等连接。 主机接口中的通信控制器实现用于与主机通信的通信协议，并且基于与主机的通信，经由对等连接将数据传送到媒体控制器和从媒体控制器传送数据。
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3.发明授权Enhanced data integrity using parallel volatile and non-volatile transfer buffers 有权使用并行易失性和非易失性传输缓冲区增强数据完整性公开(公告)号：US07549021B2
公开(公告)日：2009-06-16
申请号：US11359348
申请日：2006-02-22
CPC分类号： G11B5/09 , G06F12/0804 , G06F12/0866 , G06F2212/2022
摘要： Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block for subsequent transfer to a downstream block, such as a data storage array. The controller is further configured to direct second data to the second volatile memory block for subsequent transfer to the non-volatile circular buffer. Preferably, the second volatile memory block forms a portion of a non-volatile random access memory (NVRAM) and the circular buffer is formed from a flash memory device. An intelligence block preferably controls said subsequent transfer of the second data from the second volatile memory block to the circular buffer. The second data are preferably transferred from the circular buffer to the downstream block in conjunction with the transfer of the first data.
摘要翻译： 用于传输数据的方法和装置。 该装置优选地包括第一易失性存储器块，耦合到非易失性循环缓冲器的第二易失性存储器块和被配置为将第一数据引导到第一易失性存储器块的控制器，用于随后传送到诸如数据的下游块 存储阵列。 控制器还被配置为将第二数据引导到第二易失性存储器块，以便随后传送到非易失性循环缓冲器。 优选地，第二易失性存储器块形成非易失性随机存取存储器（NVRAM）的一部分，并且循环缓冲器由闪存器件形成。 智能块优选地控制第二数据从第二易失性存储器块到循环缓冲器的所述后续传送。 结合第一数据的传送，第二数据优选地从循环缓冲器传送到下游块。
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公开(公告)号：US08892820B2
公开(公告)日：2014-11-18
申请号：US12981294
申请日：2010-12-29
IPC分类号： G06F12/00 , H04L29/08 , H04L12/861 , G06F12/08
CPC分类号： G06F12/0868 , G06F2212/264 , H04L49/90 , H04L49/9073 , H04L67/1097 , H04L67/2842 , H04L67/289
摘要： Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction.
摘要翻译： 公开了一种存储系统。 网络接口设备（NIC）从主机接收网络存储命令。 NIC可以在固态磁盘中将数据缓存到/从存储命令中。 NIC可以通过从固态磁盘提供数据而不是发起网络事务来响应未来的网络存储命令。
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5.发明授权Disk drive having a register set for providing real time position variables to a host 失效具有用于向主机提供实时位置变量的寄存器的磁盘驱动器公开(公告)号：US06654195B1
公开(公告)日：2003-11-25
申请号：US09300179
申请日：1999-04-27
IPC分类号： G06F1300
CPC分类号： G06F3/0601 , G06F2003/0697 , G11B5/012
摘要： A disk drive provides head position information as position status variables to a host. The position status variables are derived from information formatted on a disk and processed by a media controller for storage in a position register set. The position information includes both radial and circumferential position references. The disk drive is connected to the host over a host interface which enables the position information to be stored automatically in a host memory so that the host can scan the position information to determine an optimum order of data transfer commands to be sent to the disk drive. A method for selecting a next command to transmit to a disk drive employs the position variables to optimize the command selection. In an alternative method, a host selects a command to be executed by one of an array of disk drives and then determines the disk drive to receive the command based on position information variables which have been stored and updated by the disk drives in the array.
摘要翻译： 磁盘驱动器将头位置信息作为位置状态变量提供给主机。 位置状态变量从格式化在磁盘上的信息导出，并由媒体控制器进行处理，以存储在位置寄存器集中。 位置信息包括径向和周向位置参考。 磁盘驱动器通过主机接口连接到主机，该主机接口使位置信息能够自动存储在主机存储器中，使得主机可以扫描位置信息，以确定要发送到磁盘驱动器的数据传输命令的最佳顺序 。 用于选择要发送到磁盘驱动器的下一个命令的方法使用位置变量来优化命令选择。 在替代方法中，主机选择要由磁盘驱动器阵列之一执行的命令，然后基于由阵列中的磁盘驱动器存储和更新的位置信息变量来确定磁盘驱动器以接收命令。
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6.发明授权GPU computational assist for drive media waveform generation of media emulators 失效用于媒体仿真器的驱动媒体波形生成的GPU计算辅助公开(公告)号：US08499199B2
公开(公告)日：2013-07-30
申请号：US12877842
申请日：2010-09-08
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G06F11/263
摘要： Disclosed is a method and apparatus for testing devices that will be connected to a computer storage media device by generating a complex test waveform that emulates operation of the computer storage media device using at least one Graphics Processing Unit (GPU) and applying the generated complex test waveform to the device(s) being tested. The complex test waveform may be generated by calculating a plurality of discrete individual portions of the complex test waveform in parallel, in real-time, and continuously using the parallel processing features of the GPU(s). The discrete individual portions of the complex test waveform may be representative of various characteristics of the emulated computer storage media device operation such as operational characteristics of the computer storage media device, environmental effects on the computer storage media device, application of filters to the computer storage media device signal, etc. Various embodiments may generate the base data signal waveform from the emulated computer storage device such that the entire complex test waveform is calculated. Other embodiments may use a pre-existing base data signal waveform provided from another source and modify/alter the pre-existing base data signal waveform to generate the complex test waveform. When available, one or more Central Processing Units (CPUs) and/or CPU cores may also perform calculations in parallel with the calculations performed by the GPU(s).
摘要翻译： 公开了一种用于测试将连接到计算机存储介质设备的设备的方法和设备，该设备通过生成使用至少一个图形处理单元（GPU）来模拟计算机存储介质设备的操作的复杂测试波形，并且应用所生成的复合测试 正在测试的设备的波形。 复测试波形可以通过实时并行地连续地使用GPU的并行处理特征来计算复数测试波形的多个离散的各个部分来生成。 复合测试波形的离散的单独部分可以代表仿真计算机存储介质设备操作的各种特性，例如计算机存储介质设备的操作特性，对计算机存储介质设备的环境影响，向计算机存储器应用过滤器 媒体设备信号等。各种实施例可以从仿真计算机存储设备产生基本数据信号波形，从而计算整个复杂测试波形。 其他实施例可以使用从另一个源提供的预先存在的基本数据信号波形，并且修改/改变预先存在的基本数据信号波形以产生复合测试波形。 如果可用，一个或多个中央处理单元（CPU）和/或CPU内核也可以与GPU执行的计算并行执行计算。
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7.发明授权Disk drive having a sector clock that is synchronized to the angular speed of the spindle motor 有权具有与主轴电动机的角速度同步的扇区时钟的磁盘驱动器公开(公告)号：US07126776B1
公开(公告)日：2006-10-24
申请号：US10125131
申请日：2002-04-17
IPC分类号： G11B5/09
CPC分类号： G11B19/28 , G11B5/5526 , G11B5/596
摘要： The present invention compensates for variations in the angular velocity of the drive's spindle motor by periodically dropping clocks to a counter based upon the previous servo wedge-to-wedge timing. This enables a substantially constant count to be maintained between servo wedges and allows a more predictable generation of the data sector pulses. A more predictable generation of the data sector pulses enables the size of the guard band preceding each data sector to be decreased and the capacity of the disk to be correspondingly increased.
摘要翻译： 本发明通过基于先前的伺服楔形到楔形时间周期性地将时钟丢弃到计数器来补偿驱动器的主轴电动机的角速度的变化。 这使得能够在伺服楔之间保持基本恒定的计数，并允许数据扇区脉冲的更可预测的产生。 数据扇区脉冲的更可预测的生成使得能够减少每个数据扇区之前的保护频带的大小并且相应地增加磁盘的容量。
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公开(公告)号：US07613088B2
公开(公告)日：2009-11-03
申请号：US10767510
申请日：2004-01-28
IPC分类号： G11B7/00
CPC分类号： G11B27/034 , G11B20/1809 , G11B2220/2516
摘要： A method and system for interleaving storage of data streams on a rotating storage medium of a data storage device comprise dividing the storage medium into a plurality of logical zones. Each logical zone of the plurality of logical zones extends radially from an inner diameter of the storage medium to an outer diameter of the storage medium. Data from a first stream of data is written to a first logical zone of the plurality of logical zones for up to an amount of time corresponding to the rotational speed of the storage medium and the size of the first logical zone.
摘要翻译： 一种用于在数据存储设备的旋转存储介质上交织数据流的存储的方法和系统包括将存储介质分成多个逻辑区。 多个逻辑区域的每个逻辑区域从存储介质的内径径向延伸到存储介质的外径。 来自第一数据流的数据被写入多个逻辑区域的第一逻辑区域，持续时间对应于存储介质的转速和第一逻辑区的大小。
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公开(公告)号：US07196644B1
公开(公告)日：2007-03-27
申请号：US10883633
申请日：2004-07-01
IPC分类号： H03M1/06
CPC分类号： H04L25/14 , H04L1/0045 , H04L25/0292 , H04L25/03019 , H04L25/05 , H04L27/0002
摘要： A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.
摘要翻译： 信号处理系统包括用于接收模拟信号的接收器。 该系统还包括耦合到接收器的模拟 - 数字转换器（ADC）。 在一系列时间间隔中，ADC输出顺序数字代码。 每个数字代码对应于在每个采样间隔处接收的模拟信号的采样模拟值。 该系统还包括可以存储顺序数字代码的存储器，以及用于将数字代码转换为一系列二进制数据位的处理电路。 转换可以以与数字代码存储在存储器中的顺序不同的顺序执行。
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