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    Decoupling of analog input and digital output
    1.
    发明授权
    Decoupling of analog input and digital output 有权
    模拟输入和数字输出的去耦

    公开(公告)号：US07196644B1

    公开(公告)日：2007-03-27

    申请号：US10883633

    申请日：2004-07-01

    申请人： Kent D. Anderson ,  Gregory L. Silvus ,  Robert W. Warren, Jr.

    发明人： Kent D. Anderson ,  Gregory L. Silvus ,  Robert W. Warren, Jr.

    IPC分类号： H03M1/06

    CPC分类号： H04L25/14 ,  H04L1/0045 ,  H04L25/0292 ,  H04L25/03019 ,  H04L25/05 ,  H04L27/0002

    摘要： A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.

    摘要翻译： 信号处理系统包括用于接收模拟信号的接收器。 该系统还包括耦合到接收器的模拟 - 数字转换器（ADC）。 在一系列时间间隔中，ADC输出顺序数字代码。 每个数字代码对应于在每个采样间隔处接收的模拟信号的采样模拟值。 该系统还包括可以存储顺序数字代码的存储器，以及用于将数字代码转换为一系列二进制数据位的处理电路。 转换可以以与数字代码存储在存储器中的顺序不同的顺序执行。

    Write jog value determination for a disk drive
    4.
    发明授权
    Write jog value determination for a disk drive 有权
    为磁盘驱动器写入点动值确定

    公开(公告)号：US08000053B1

    公开(公告)日：2011-08-16

    申请号：US12343285

    申请日：2008-12-23

    申请人： Kent D. Anderson

    发明人： Kent D. Anderson

    IPC分类号： G11B5/455

    CPC分类号： G11B5/012 ,  B82Y10/00 ,  G11B5/455 ,  G11B5/5534 ,  G11B5/59627 ,  G11B5/743 ,  G11B2005/0005

    摘要： A disk drive for determining a write jog value is disclosed. The disk drive comprises: a disk; a head including a reader and a writer; and a processor. The processor controls operations in the disk drive including: commanding the reader to track follow on a first track, wherein the writer is located over an uncalibrated track position; commanding the writer to write a first test pattern on a section of the disk; commanding the writer to move by a plurality of step amounts to write a plurality of test patterns; commanding the reader to move by a second plurality of step amounts to read the plurality of test patterns; determining a reader signal value associated with each test pattern; determining the uncalibrated track position based on the read signal values; and determining the write jog value based on the distance between the first track and the uncalibrated track position.

    摘要翻译： 公开了一种用于确定写入点动值的磁盘驱动器。 磁盘驱动器包括：磁盘; 包括读者和作家的头衔; 和处理器。 处理器控制磁盘驱动器中的操作，包括：命令读取器跟踪第一轨道，其中写入器位于未校准的轨道位置上; 命令写入器在磁盘的一部分上写入第一个测试模式; 命令写入器移动多个步骤量以写入多个测试图案; 命令读取器移动第二多个步骤量以读取多个测试图案; 确定与每个测试图案相关联的阅读器信号值; 基于读取的信号值确定未校准的轨道位置; 以及基于第一轨道和未校准轨道位置之间的距离来确定写入点动值。

    SYNCHRONOUS READ CHANNEL
    5.
    发明申请
    SYNCHRONOUS READ CHANNEL 失效
    同步读通道

    公开(公告)号：US20080285549A1

    公开(公告)日：2008-11-20

    申请号：US12126188

    申请日：2008-05-23

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    IPC分类号： H04L12/50

    CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。