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公开(公告)号：US07026846B1
公开(公告)日：2006-04-11
申请号：US10888144
申请日：2004-07-09
IPC分类号： G06F1/02
CPC分类号： G06F1/022
摘要： Synthesizers are provided to generate synthesizer signals in response to primary digital signal representations that are created by a signal generator. In an important feature, the synthesizers further include a signal corrector that inserts correction digital signal representations to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.
摘要翻译： 提供合成器以响应由信号发生器产生的主数字信号表示而产生合成器信号。 在一个重要特征中，合成器还包括一个信号校正器，其插入校正数字信号表示以至少部分地消除主数字信号表示中相应的杂散分量，从而提供具有减少的杂散内容的合成器信号。
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公开(公告)号：US5706008A
公开(公告)日：1998-01-06
申请号：US609651
申请日：1996-03-01
CPC分类号： H03M1/0682 , H03M1/363
摘要： A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signals are superimposed upon the ladders by drivers which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC.
摘要翻译： 新的差分梯形图/比较器电路减少并行模数转换器的稳定时间延迟。 并行模数转换器（ADC）包括一对具有连接到一组比较器的抽头的差分电阻梯。 比较器产生对应于印在差分梯子上的模拟信号的数字“温度计”刻度输出。 通过采用双值电阻器来形成梯子的“梯级”，并通过将比较器连接到梯形抽头，以增加连接到梯级低阶抽头的比较器输入的数量并减少比较器输入的数量 连接到梯子的高阶抽头，与传统的差分梯形并行ADC相比，梯形图/比较器组合所呈现的输入阻抗减小。 此外，输入信号通过驱动器叠加在梯子上，在优选实施例中，驱动器向梯子提供比现有技术驱动器更低的输出阻抗，进一步提高了ADC的带宽。
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