公开(公告)号：US07026846B1

公开(公告)日：2006-04-11

申请号：US10888144

申请日：2004-07-09

申请人： Roger B. Huntley, Jr. ,  Jon T. Baird ,  David T. Crook ,  Ken Gentile ,  Reuben P. Nelson

发明人： Roger B. Huntley, Jr. ,  Jon T. Baird ,  David T. Crook ,  Ken Gentile ,  Reuben P. Nelson

IPC分类号： G06F1/02

CPC分类号： G06F1/022

摘要： Synthesizers are provided to generate synthesizer signals in response to primary digital signal representations that are created by a signal generator. In an important feature, the synthesizers further include a signal corrector that inserts correction digital signal representations to at least partially cancel a corresponding spurious component in the primary digital signal representation and thereby provide synthesizer signals with reduced spurious content.

摘要翻译： 提供合成器以响应由信号发生器产生的主数字信号表示而产生合成器信号。 在一个重要特征中，合成器还包括一个信号校正器，其插入校正数字信号表示以至少部分地消除主数字信号表示中相应的杂散分量，从而提供具有减少的杂散内容的合成器信号。

公开(公告)号：US06621366B1

公开(公告)日：2003-09-16

申请号：US10013131

申请日：2001-12-07

申请人： Ken Gentile

发明人： Ken Gentile

IPC分类号： H03C300

CPC分类号： H03C3/40

摘要： In order to generate a carrier frequency Fc, a digital modulator must operate (to satisfy the Nyquist criteria) at a system sample rate Rs which is at least twice the carrier frequency Fc. However, digital modulator structures are provided herein that facilitate the use of M quadrature modulators which modulate, at a reduced modulation rate Rs/M, respective ones of M polyphase cosine elements and M polyphase sine elements with respective ones of interpolated I elements and interpolated Q elements to thereby form M polyphase modulated elements. The modulated elements are then sequentially selected in a multiplexer to form a modulated digital signal. The reduced modulation rate simplifies modulator design and lowers fabrication costs.

摘要翻译： 为了产生载波频率Fc，数字调制器必须以至少是载波频率Fc的两倍的系统采样率Rs操作（以满足奈奎斯特准则）。 然而，本文提供的数字调制器结构有助于使用M个正交调制器，其以降低的调制速率Rs / M调制M个多相余弦元素和M个多相正弦元件中的相应内插I元素和内插Q 从而形成M多相调制元件。 然后在多路复用器中顺序选择调制元件以形成调制数字信号。 降低的调制速率简化了调制器设计并降低了制造成本。

公开(公告)号：US4977530A

公开(公告)日：1990-12-11

申请号：US189180

申请日：1988-05-02

申请人： John Cline ,  Ken Gentile

发明人： John Cline ,  Ken Gentile

IPC分类号： G01R31/28

CPC分类号： G01R31/2834

摘要： In a circuit tester for applying test voltage to circuit components, a voltage monitor for detecting potentially destructive voltages being applied to one or more additional circuit components other than the components being tested, and in response generating an alarm signal for interrupting the circuit tester, thereby inhibiting generation of the destructive voltages. Monitored input voltages are compared to selectable positive and negative threshold voltages defining upper and lower polarity sensitive destructive voltage limits.

摘要翻译： 在用于向电路部件施加测试电压的电路测试器中，用于检测潜在的破坏性电压的电压监视器被施加到除被测试部件之外的一个或多个附加电路部件，并且响应于产生用于中断电路测试器的报警信号，从而 抑制破坏性电压的产生。 将监控的输入电压与定义上限和下限极性敏感的破坏性电压限制的可选正和负阈值电压进行比较。

公开(公告)号：US07180384B2

公开(公告)日：2007-02-20

申请号：US11136012

申请日：2005-05-23

申请人： Dimitrios Efstathiou ,  Ken Gentile

发明人： Dimitrios Efstathiou ,  Ken Gentile

IPC分类号： H03K7/00

CPC分类号： H04L27/362 ,  H04L27/361

摘要： Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

摘要翻译： 示出了通用信号调制器结构，其特别适用于从输入相位和幅度符号选择性地产生极调调制数字序列，并且用于从输入的第一和第二正交符号产生正交调制的数字序列。 重要的是，通过简单地改变模式命令的状态来选择这些实施例的调制结构（正交调制或极坐标调制）。

公开(公告)号：US20060261907A1

公开(公告)日：2006-11-23

申请号：US11136012

申请日：2005-05-23

申请人： Dimitrios Efstathiou ,  Ken Gentile

发明人： Dimitrios Efstathiou ,  Ken Gentile

IPC分类号： H03K7/00

CPC分类号： H04L27/362 ,  H04L27/361

摘要： Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

摘要翻译： 示出了通用信号调制器结构，其特别适用于从输入相位和幅度符号选择性地产生极调调制数字序列，并且用于从输入的第一和第二正交符号产生正交调制的数字序列。 重要的是，通过简单地改变模式命令的状态来选择这些实施例的调制结构（正交调制或极坐标调制）。

公开(公告)号：US07788309B2

公开(公告)日：2010-08-31

申请号：US11398213

申请日：2006-04-04

申请人： Lu Wu ,  Ken Gentile

发明人： Lu Wu ,  Ken Gentile

IPC分类号： G06F17/17

CPC分类号： H03H17/0671 ,  H03H2017/0678

摘要： Filter system embodiments are provided for realizing interpolation and decimation processes with interleaved filter structures. These interleaved structures enable the systems to obtain output data rates that exceed the highest operation rates of the system components.

摘要翻译： 滤波器系统实施例被提供用于实现具有交错滤波器结构的插值和抽取处理。 这些交错结构使得系统能够获得超过系统组件的最高操作速率的输出数据速率。

公开(公告)号：US07034624B1

公开(公告)日：2006-04-25

申请号：US10734391

申请日：2003-12-11

申请人： Ken Gentile

发明人： Ken Gentile

IPC分类号： H03L7/00

CPC分类号： H03L7/183 ,  H03L2207/50

摘要： Signal generators are realized with combinations of a digital synthesizer (e.g., direct digital synthesizer), a frequency controller and a phase controller. The frequency controller receives a user-provided minimum count of a reference frequency wherein the minimum count is chosen to initially position a synthesizer signal within a selected frequency error of the reference frequency. In response, the frequency controller runs counters over a time sufficient to obtain the minimum count. The frequency controller then uses a difference count between the counts of the reference frequency and the synthesizer frequency to determine a controlled tuning word that properly positions the synthesizer signal. Subsequently, the phase controller detects phase differences between the reference signal and the synthesizer signal and applies phase correction signals to control the phase of the synthesizer signal.

摘要翻译： 信号发生器通过数字合成器（例如，直接数字合成器），频率控制器和相位控制器的组合来实现。 频率控制器接收用户提供的参考频率的最小计数，其中选择最小计数以将合成器信号初始定位在参考频率的选定频率误差内。 作为响应，频率控制器运行计数器足够长的时间以获得最小计数。 然后，频率控制器使用参考频率和合成器频率的计数之间的差分计数来确定适当地定位合成器信号的受控调谐字。 随后，相位控制器检测参考信号和合成器信号之间的相位差，并施加相位校正信号以控制合成器信号的相位。

公开(公告)号：US07013319B1

公开(公告)日：2006-03-14

申请号：US09989283

申请日：2001-11-20

申请人： Ken Gentile

发明人： Ken Gentile

IPC分类号： G06F17/10

CPC分类号： H03H17/06 ,  H03H17/0223 ,  H03H2017/0247

摘要： Digital filters are provided that include a converter and a data processor. The converter converts successive strings of M successive data elements that occur at a system rate Fs in an input data stream Din to M parallel data elements that respectively occur at a substream rate Fs/M in M data substreams Dsbstrm. At a reduced substream rate Fs/M, the processor generates M convolutions of the filter's quantized impulse response with the M data substreams wherein each of the convolutions is arranged to generate a different one of M successive filtered output signals. Because the convolutions are conducted at the reduced substream rate Fs/M, the filters can operate at increased system rates. Preferably, the digital filter also includes a multiplexer that selects, at the system rate Fs, the M filtered output signals in successive order to thereby form a filtered output data stream Dout.

摘要翻译： 提供了包括转换器和数据处理器的数字滤波器。 转换器将在中的输入数据流D 中以系统速率F S发生的M个连续数据元素的连续字符串转换为分别在子流中发生的M个并行数据元素 速率F S / S / M在M个数据子流D Sbstrm 中。 在减少的子流速率F N / M，处理器产生M个数据子流的滤波器的量化脉冲响应的M个卷积，其中每个卷积被布置成产生M个连续滤波输出中的不同的一个 信号。 由于卷积以降低的子流速率F N / M进行，滤波器可以以增加的系统速率工作。 优选地，数字滤波器还包括多路复用器，其以系统速率F S连续地选择M个经过滤波的输出信号，从而形成滤波后的输出数据流D 。

公开(公告)号：US20070230642A1

公开(公告)日：2007-10-04

申请号：US11398213

申请日：2006-04-04

申请人： Lu Wu ,  Ken Gentile

发明人： Lu Wu ,  Ken Gentile

IPC分类号： H04B1/10

CPC分类号： H03H17/0671 ,  H03H2017/0678

摘要： Filter system embodiments are provided for realizing interpolation and decimation processes with interleaved filter structures. These interleaved structures enable the systems to obtain output data rates that exceed the highest operation rates of the system components.

摘要翻译： 滤波器系统实施例被提供用于实现具有交错滤波器结构的插值和抽取处理。 这些交错结构使得系统能够获得超过系统组件的最高操作速率的输出数据速率。

公开(公告)号：US06587863B1

公开(公告)日：2003-07-01

申请号：US09605099

申请日：2000-06-27

申请人： Ken Gentile ,  John Kornblum

发明人： Ken Gentile ,  John Kornblum

IPC分类号： G06F102

CPC分类号： G06F1/0328

摘要： Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;s. This method comprises the steps of a) with a count capacity C, counting modulo n&phgr;s at a reduced clock frequency (1/n)fclk to thereby generate a primary substream of digital words, b) phase offsetting the primary substream to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step &phgr;s, c) converting the digital words of each of the primary, and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform, and d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency fclk.

摘要翻译： 提供直接数字合成（DDS）方法和结构，其增加DDS输出频率fout，而不需要DDS结构必须操作的速率fclk的相应增加。 一种示例性方法在时钟频率fclk处产生数字字的周期性流，其中字表示预定周期波形的各个幅度，周期流具有周期P，数字字由相位步长隔开。 该方法包括以下步骤：a）具有计数能力C，以降低的时钟频率（1 / n）fclk对模数nphis进行计数，从而产生数字字的主子流，b）相位偏移主子流以形成n-1 数字字的二次子流，其中主和次级子流由相位步长相位相隔，c）将主和次级子流中的每一个的数字字转换成表示预定波形的各个幅度的转换数字字，d ）对主流和次级流进行交织，从而形成在时钟频率fclk出现的数字字的周期流。