公开(公告)号：US08222926B2

公开(公告)日：2012-07-17

申请号：US12279467

申请日：2007-01-18

申请人： Rolf Sundblad ,  Staffan Gustafsson

发明人： Rolf Sundblad ,  Staffan Gustafsson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  H03K17/161

摘要： A track and hold circuit (1) comprising a switch device (10) and a capacitive hold device (20). The track and hold circuit (1) comprises a track-voltage generating device (30) adapted to generate a control voltage based on a signal on an input terminal of the switch device (10) and supply the control voltage to the switch device (10) during track phases of the track and hold circuit (1). The control voltage provides a channel charge, which is the same for each track phase, in the switch device (10).

摘要翻译： 一种包括开关装置（10）和电容性保持装置（20）的跟踪和保持电路（1）。 轨道保持电路（1）包括轨道电压产生装置（30），其适于基于开关装置（10）的输入端上的信号产生控制电压，并将控制电压提供给开关装置（10） ）在轨道和保持电路（1）的轨道相位期间。 控制电压在开关装置（10）中提供每个轨道相位的通道电荷。

公开(公告)号：US08344759B2

公开(公告)日：2013-01-01

申请号：US13545690

申请日：2012-07-10

申请人： Rolf Sundblad ,  Staffan Gustafsson

发明人： Rolf Sundblad ,  Staffan Gustafsson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  H03K17/161

摘要： A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.

摘要翻译： 一种跟踪和保持电路，包括开关器件和电容保持器件。 轨道和保持电路包括轨道电压产生装置，其适于基于开关装置的输入端上的信号产生控制电压，并且在轨道和保持电路的轨道相位期间将控制电压提供给开关装置。 控制电压为开关装置中的每个磁道相位提供通道电荷。

公开(公告)号：US20120280722A1

公开(公告)日：2012-11-08

申请号：US13545690

申请日：2012-07-10

申请人： Rolf Sundblad ,  Staffan Gustafsson

发明人： Rolf Sundblad ,  Staffan Gustafsson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  H03K17/161

摘要： A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.

摘要翻译： 一种跟踪和保持电路，包括开关器件和电容保持器件。 轨道和保持电路包括轨道电压产生装置，其适于基于开关装置的输入端上的信号产生控制电压，并且在轨道和保持电路的轨道相位期间将控制电压提供给开关装置。 控制电压为开关装置中的每个磁道相位提供通道电荷。

公开(公告)号：US20090206885A1

公开(公告)日：2009-08-20

申请号：US12279467

申请日：2007-01-18

申请人： Rolf Sundblad ,  Staffan Gustafsson

发明人： Rolf Sundblad ,  Staffan Gustafsson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  H03K17/161

摘要： A track and hold circuit (1) comprising a switch device (10) and a capacitive hold device (20). The track and hold circuit (1) comprises a track-voltage generating device (30) adapted to generate a control voltage based on a signal on an input terminal of the switch device (10) and supply the control voltage to the switch device (10) during track phases of the track and hold circuit (1). The control voltage provides a channel charge, which is the same for each track phase, in the switch device (10).

摘要翻译： 一种包括开关装置（10）和电容性保持装置（20）的跟踪和保持电路（1）。 轨道保持电路（1）包括轨道电压产生装置（30），其适于基于开关装置（10）的输入端上的信号产生控制电压，并将控制电压提供给开关装置（10） ）在轨道和保持电路（1）的轨道相位期间。 控制电压在开关装置（10）中提供每个轨道相位的通道电荷。

公开(公告)号：US20110243290A1

公开(公告)日：2011-10-06

申请号：US13063286

申请日：2009-09-09

申请人： Graham R. Leach ,  Gordon A. Wilson ,  Rolf Sundblad

发明人： Graham R. Leach ,  Gordon A. Wilson ,  Rolf Sundblad

IPC分类号： H03D3/24

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/099

摘要： A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider (50) is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider (60) is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.

摘要翻译： 一种用于基于hsync信号产生像素时钟信号的PLL电路（1a，1b）。 PLL电路包括相位频率检测器，被配置为接收hsync信号和分频像素时钟信号，并且基于hsync信号和分频像素时钟信号产生上下信号。 电荷泵（20）被布置成基于上下信号产生输出信号，并且环路滤波器（30）被布置成基于电荷泵（20）的输出信号产生频率控制信号。 此外，VCO（40a，40b）被布置成响应于频率控制信号产生振荡信号并调整振荡信号的频率。 VCO（40a，40b）适于具有大于或等于4GHz的中心频率的调谐范围。 可编程第一分频器（50）被布置成通过振荡信号的分频产生像素时钟信号，并且可编程第二分频器（60）被布置成通过对频率分频器 像素时钟信号。

公开(公告)号：US08009071B2

公开(公告)日：2011-08-30

申请号：US12636249

申请日：2009-12-11

申请人： Rolf Sundblad

发明人： Rolf Sundblad

IPC分类号： H03M1/00

CPC分类号： H03F3/45475 ,  H03F3/45928 ,  H03F2203/45512 ,  H03F2203/45526 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45544 ,  H03F2203/45546 ,  H03F2203/45594 ,  H03F2203/45618

摘要： A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (Vref, Vcm,ref) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

摘要翻译： 增益电路包括主放大单元和第一刷新单元。 主放大单元包括放大器，连接在增益电路的第一输入端和放大器的第一输入端之间的第一电容器和连接在放大器的第一输入端和第二输出端之间的第二电容器， 放大器 第一刷新单元包括与第一电容器的第一端子连接到第一刷新单元的公共节点的第一电容器和与第二电容器的第一端子连接到第一刷新单元的公共节点的第二电容器。 第一刷新电路的公共节点布置成在刷新间隔的第一阶段期间被提供参考电压（Vref，Vcm，ref），并且在刷新间隔的第二阶段期间连接到放大器的第一输入端 。

公开(公告)号：US08212697B2

公开(公告)日：2012-07-03

申请号：US12815882

申请日：2010-06-15

申请人： Christer Jansson ,  Rolf Sundblad

发明人： Christer Jansson ,  Rolf Sundblad

IPC分类号： H03M1/06

CPC分类号： H03M1/1019 ,  H03M1/1215

摘要： An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

摘要翻译： 公开了一种具有多个计算通道并且适于将来自模拟域的信号转换为数字域的时间交织的模数转换器的偏移补偿的装置。 该装置包括时间交织的模拟 - 数字转换器，适于估计多个计算通道的平均偏移量的模拟偏移估计和补偿单元，适用于估计残差计算通道特定偏移的数字偏移估计和补偿单元 对于多个计算通道中的每一个以及偏移补偿装置。 偏移补偿装置适于基于模拟域中估计的平均偏移在多个信道中的每一个的模拟域中执行偏移补偿，并且在多个信道中的每一个的数字域中基于 相应的残差计算通道的特定偏移量。

公开(公告)号：US07649394B2

公开(公告)日：2010-01-19

申请号：US12279392

申请日：2007-01-18

申请人： Rolf Sundblad

发明人： Rolf Sundblad

IPC分类号： H03K3/00

CPC分类号： H03K3/356139

摘要： A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a current generated by the first input device (10a) and a second estimator unit (40b) adapted to generate a second estimate of a current generated by the second input device (10b). The latch circuit further comprises a control-voltage unit (50) operatively connected to the first and the second estimator unit (40a, 40b). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit (1) comprises a first and a second voltage-controlled current unit (30a, 30b) adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit (30a) is operatively connected to the first branch (4a). The second voltage-controlled current unit (30b) is operatively connected to the second branch (4b). A method for compensation for common-mode variations in the latch circuit (1) is also disclosed.

摘要翻译： 一种锁存电路（1），包括在第一分支（4a）中的第一输入装置（10a）和第二分支（4b）中的第二输入装置（10b）。 锁存电路包括适于产生由第一输入装置（10a）产生的电流的第一估计的第一估计器单元（40a）和适于产生由第二输入装置（10a）产生的电流的第二估计的第二估计器单元（40b） 输入装置（10b）。 锁存电路还包括可操作地连接到第一和第二估计器单元（40a，40b）的控制电压单元（50）。 控制电压单元适于基于第一估计和第二估计的和产生控制电压。 此外，锁存电路（1）包括适于至少基于控制电压产生电流的第一和第二电压控制电流单元（30a，30b）。 第一电压控制电流单元（30a）可操作地连接到第一分支（4a）。 第二电压控制电流单元（30b）可操作地连接到第二分支（4b）。 还公开了一种用于补偿锁存电路（1）中的共模变化的方法。

公开(公告)号：US08576970B2

公开(公告)日：2013-11-05

申请号：US13063286

申请日：2009-09-09

申请人： Graham R. Leach ,  Gordon A. Wilson ,  Rolf Sundblad

发明人： Graham R. Leach ,  Gordon A. Wilson ,  Rolf Sundblad

IPC分类号： H03D3/24

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/099

摘要： A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider (50) is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider (60) is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.

摘要翻译： 一种用于基于hsync信号产生像素时钟信号的PLL电路（1a，1b）。 PLL电路包括相位频率检测器，被配置为接收hsync信号和分频像素时钟信号，并且基于hsync信号和分频像素时钟信号产生上下信号。 电荷泵（20）被布置成基于上下信号产生输出信号，并且环路滤波器（30）被布置成基于电荷泵（20）的输出信号产生频率控制信号。 此外，VCO（40a，40b）被布置成响应于频率控制信号产生振荡信号并调整振荡信号的频率。 VCO（40a，40b）适于具有大于或等于4GHz的中心频率的调谐范围。 可编程第一分频器（50）被布置成通过振荡信号的分频产生像素时钟信号，并且可编程第二分频器（60）被布置成通过频率分频产生分频像素时钟信号 像素时钟信号。

公开(公告)号：US20090066387A1

公开(公告)日：2009-03-12

申请号：US12279392

申请日：2007-01-18

申请人： Rolf Sundblad

发明人： Rolf Sundblad

IPC分类号： H03K3/356 ,  H03K3/289

CPC分类号： H03K3/356139

摘要： A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a current generated by the first input device (10a) and a second estimator unit (40b) adapted to generate a second estimate of a current generated by the second input device (10b). The latch circuit further comprises a control-voltage unit (50) operatively connected to the first and the second estimator unit (40a, 40b). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit (1) comprises a first and a second voltage-controlled current unit (30a, 30b) adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit (30a) is operatively connected to the first branch (4a). The second voltage-controlled current unit (30b) is operatively connected to the second branch (4b). A method for compensation for common-mode variations in the latch circuit (1) is also disclosed.

摘要翻译： 一种锁存电路（1），包括在第一分支（4a）中的第一输入装置（10a）和第二分支（4b）中的第二输入装置（10b）。 锁存电路包括适于产生由第一输入装置（10a）产生的电流的第一估计的第一估计器单元（40a）和适于产生由第二输入装置（10a）产生的电流的第二估计的第二估计器单元（40b） 输入装置（10b）。 锁存电路还包括可操作地连接到第一和第二估计器单元（40a，40b）的控制电压单元（50）。 控制电压单元适于基于第一估计和第二估计的和产生控制电压。 此外，锁存电路（1）包括适于至少基于控制电压产生电流的第一和第二电压控制电流单元（30a，30b）。 第一电压控制电流单元（30a）可操作地连接到第一分支（4a）。 第二电压控制电流单元（30b）可操作地连接到第二分支（4b）。 还公开了一种用于补偿锁存电路（1）中的共模变化的方法。