CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof
    1.
    发明申请
    CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof 有权
    用于降低电荷共享效应的CMOS器件及其制造方法

    公开(公告)号:US20130161757A1

    公开(公告)日:2013-06-27

    申请号:US13582034

    申请日:2012-04-16

    IPC分类号: H01L27/092 H01L21/8238

    摘要: The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.

    摘要翻译: 本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。 本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。 附加隔离区的材料是多孔硅。 由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料,因此在多孔硅的表面层上存在大量微孔和悬挂键。 这些缺陷可能在多孔硅的禁带的中心形成缺陷状态,缺陷状态可能会捕获载体以引起增加的电阻。 随着腐蚀电流密度的增加,孔隙率增加,多孔硅中的缺陷增加。 本发明可以通过使用多孔硅捕集载体中的缺陷状态,浅沟槽隔离(STI)区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应, 并且该工艺简单,从而可以大大提高集成电路的射电阻性能。

    CMOS DEVICE FOR REDUCING RADIATION-INDUCED CHARGE COLLECTION AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    CMOS DEVICE FOR REDUCING RADIATION-INDUCED CHARGE COLLECTION AND METHOD FOR FABRICATING THE SAME 有权
    用于减少辐射诱导电荷收集的CMOS器件及其制造方法

    公开(公告)号:US20130119445A1

    公开(公告)日:2013-05-16

    申请号:US13509170

    申请日:2011-11-30

    IPC分类号: H01L29/78 H01L21/336

    摘要: A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

    摘要翻译: 用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。 在CMOS器件中,重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。 该区域具有与源极区域和漏极区域相反的掺杂类型,并且具有不小于源极区域和漏极区域的掺杂浓度。 电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分,并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围,使得可以在电场的力作用下立即收集的电荷减少。

    CMOS device for reducing radiation-induced charge collection and method for fabricating the same
    3.
    发明授权
    CMOS device for reducing radiation-induced charge collection and method for fabricating the same 有权
    用于减少辐射诱导的电荷收集的CMOS器件及其制造方法

    公开(公告)号:US08877594B2

    公开(公告)日:2014-11-04

    申请号:US13509170

    申请日:2011-11-30

    摘要: A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

    摘要翻译: 用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。 在CMOS器件中,重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。 该区域具有与源极区域和漏极区域相反的掺杂类型,并且具有不小于源极区域和漏极区域的掺杂浓度。 电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分,并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围,使得可以在电场的力作用下立即收集的电荷减少。

    CMOS device for reducing charge sharing effect and fabrication method thereof
    4.
    发明授权
    CMOS device for reducing charge sharing effect and fabrication method thereof 有权
    用于降低电荷共享效应的CMOS器件及其制造方法

    公开(公告)号:US08652929B2

    公开(公告)日:2014-02-18

    申请号:US13582034

    申请日:2012-04-16

    摘要: The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.

    摘要翻译: 本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。 本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。 附加隔离区的材料是多孔硅。 由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料,因此在多孔硅的表面层上存在大量微孔和悬挂键。 这些缺陷可能在多孔硅的禁带的中心形成缺陷状态,缺陷状态可能会捕获载体以引起增加的电阻。 随着腐蚀电流密度的增加,孔隙率增加,多孔硅中的缺陷增加。 本发明可以通过使用多孔硅捕集载体中的缺陷状态,浅沟槽隔离(STI)区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应, 并且该工艺简单,从而可以大大提高集成电路的射电阻性能。

    METHOD FOR OBTAINING DISTRIBUTION OF CHARGES ALONG CHANNEL IN MOS TRANSISTOR
    5.
    发明申请
    METHOD FOR OBTAINING DISTRIBUTION OF CHARGES ALONG CHANNEL IN MOS TRANSISTOR 审中-公开
    用于获取MOS晶体管中的通道分配的方法

    公开(公告)号:US20130013245A1

    公开(公告)日:2013-01-10

    申请号:US13499275

    申请日:2011-10-28

    IPC分类号: G01R31/26 G06F19/00

    CPC分类号: G01R31/2621 H01L22/14

    摘要: The present invention discloses a method for obtaining a distribution of charges along a channel of a MOS transistor, which is used for obtaining distributions of interface states charges and charges of a gate dielectric layer in the MOS transistor. The method includes: adding a MOS transistor into a test circuit; measuring two charge pumping current curves when a source terminal is open-circuited or when a drain terminal is open-circuited before and after a stress is applied by using a charge pumping current test method, where one of the two charge pumping current curves is an original curve and the other one is an post-stress curve; finding a point B corresponding to a point A on the original curve on the post-stress curve, and estimating amount of locally-generated interface states charges and charges of the gate dielectric layer by a variation of the charge pumping current and a variation in a voltage at a local point. As compared with a conventional method for obtaining a distribution, the method of the present invention can obtain a distribution of charges along a direction form the drain or source terminal to the channel more easily and rapidly, with an aid of a computer. A mass of complicated and repeated tests are reduced. Also, the method can provide an effective base for improving device reliability.

    摘要翻译: 本发明公开了一种用于获得沿着MOS晶体管的沟道的电荷分布的方法,用于获得MOS晶体管中的界面态电荷和栅介质层的电荷的分布。 该方法包括:将MOS晶体管添加到测试电路中; 当源极端子开路时,或者在通过使用电荷泵浦电流测试方法施加应力之前和之后漏极端子开路时,测量两个电荷泵浦电流曲线,其中两个电荷泵浦电流曲线之一为 原曲线,另一个是后应力曲线; 找到对应于后应力曲线上的原始曲线上的点A的点B,并且通过电荷泵浦电流的变化和局部产生的界面的变化来估计局部产生的界面状态的电介质层的电荷和电荷 电压在本地点。 与用于获得分布的常规方法相比,本发明的方法可以借助于计算机,更容易和快速地获得沿着从漏极或源极端子到达通道的方向的电荷分布。 大量复杂和重复的测试减少了。 此外,该方法可以提供用于提高装置可靠性的有效基础。

    SYSTEM AND METHOD FOR GENERATING CONTROL INSTRUCTION BY USING IMAGE PICKUP DEVICE TO RECOGNIZE USERS POSTURE
    6.
    发明申请
    SYSTEM AND METHOD FOR GENERATING CONTROL INSTRUCTION BY USING IMAGE PICKUP DEVICE TO RECOGNIZE USERS POSTURE 审中-公开
    使用图像拾取装置识别使用者的控制指令的系统和方法

    公开(公告)号:US20110158546A1

    公开(公告)日:2011-06-30

    申请号:US12723417

    申请日:2010-03-12

    IPC分类号: G06K9/62

    摘要: A system and a method are provided for generating a control instruction by using an image pickup device to recognize a user's posture. An electronic device is controlled according to different composite postures. Each composite posture is a combination of the hand posture, the head posture and the facial expression change of the user. Each composite posture indicates a corresponding control instruction. Since the composite posture is more complex than peoples' habitual actions, the possibility of causing erroneous control instruction from unintentional habitual actions of the user will be minimized or eliminated.

    摘要翻译: 提供了一种系统和方法,用于通过使用图像拾取装置来识别用户的姿势来产生控制指令。 根据不同的复合姿势控制电子设备。 每个复合姿势是用户的手势,头部姿势和面部表情变化的组合。 每个复合姿势指示相应的控制指令。 由于复合姿势比人们的习惯动作更为复杂,因此可能会最大限度地减少或消除由用户无意的习惯性动作导致错误控制指令的可能性。