公开(公告)号：US08158474B2

公开(公告)日：2012-04-17

申请号：US12873889

申请日：2010-09-01

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L21/0243 ,  H01L23/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US07825477B2

公开(公告)日：2010-11-02

申请号：US11738968

申请日：2007-04-23

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L23/62 ,  H01L29/78 ,  H01L21/0234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US20100330755A1

公开(公告)日：2010-12-30

申请号：US12873889

申请日：2010-09-01

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US20080258233A1

公开(公告)日：2008-10-23

申请号：US11738968

申请日：2007-04-23

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US08778717B2

公开(公告)日：2014-07-15

申请号：US12726215

申请日：2010-03-17

申请人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

发明人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC分类号： H01L21/00

CPC分类号： H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

摘要翻译： 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

公开(公告)号：US08546860B2

公开(公告)日：2013-10-01

申请号：US13494769

申请日：2012-06-12

申请人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L31/113 ,  H01L31/173

CPC分类号： H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

摘要： This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.

摘要翻译： 本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。 有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。 有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。 有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色 细胞计数由第一次压力引起。

公开(公告)号：US08216905B2

公开(公告)日：2012-07-10

申请号：US12768063

申请日：2010-04-27

申请人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L21/336

CPC分类号： H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

摘要： The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

摘要翻译： 上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。 制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。 通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。 如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。 拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

公开(公告)号：US20110230002A1

公开(公告)日：2011-09-22

申请号：US12726215

申请日：2010-03-17

申请人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

发明人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC分类号： H01L21/26

CPC分类号： H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

摘要翻译： 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入到硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

公开(公告)号：US08389316B2

公开(公告)日：2013-03-05

申请号：US13089765

申请日：2011-04-19

申请人： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

发明人： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

摘要： A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

摘要翻译： 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US20110195554A1

公开(公告)日：2011-08-11

申请号：US13089765

申请日：2011-04-19

申请人： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

发明人： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

摘要： A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

摘要翻译： 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。