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1.发明授权Special purpose memory for graphics and display apparatus using the special purpose memory for graphics 失效用于图形和显示设备的专用存储器，使用专用存储器进行图形处理
公开(公告)号：US5801706A
公开(公告)日：1998-09-01
申请号：US425514
申请日：1995-04-20
申请人： Ryo Fujita , Mitsuru Soga , Yasushi Fukunaga , Takehiko Nishida
发明人： Ryo Fujita , Mitsuru Soga , Yasushi Fukunaga , Takehiko Nishida
CPC分类号： G06T15/005 , G06T1/60 , G09G5/393 , G09G5/395
摘要： A three-dimensional graphic display apparatus performs hidden surface removal and color blending. Particularly, the graphic display apparatus includes a configuration of a special purpose memory for graphics, thereby forming a configuration of a graphic display apparatus using the special purpose memory. The special purpose memory for graphics includes a memory cell holding intensity information (RGB) and window information about each pixel, an XY coordinate converter converting XY coordinates of a pixel to be written to a memory address, an intensity blending processor, and hidden-surface removal and window comparators, all of which are formed on the same chip.
摘要翻译： 三维图形显示装置执行隐藏的表面去除和颜色混合。 特别地，图形显示装置包括用于图形的专用存储器的配置，从而形成使用专用存储器的图形显示装置的配置。 用于图形的专用存储器包括存储单元保持强度信息（RGB）和关于每个像素的窗口信息，XY坐标转换器将要写入的像素的XY坐标转换到存储器地址，强度混合处理器和隐藏表面 去除和窗口比较器，它们都在同一个芯片上形成。
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2.发明授权
公开(公告)号：US5917496A
公开(公告)日：1999-06-29
申请号：US59397
申请日：1998-04-14
申请人： Ryo Fujita , Mitsuru Soga , Yasushi Fukunaga , Takehiko Nishida
发明人： Ryo Fujita , Mitsuru Soga , Yasushi Fukunaga , Takehiko Nishida
CPC分类号： G06T15/005 , G06T1/60 , G09G5/393 , G09G5/395
摘要： The present invention relates to a three-dimensional graphic display apparatus for performing a hidden surface removal and color blending, and particularly to a configuration of a special purpose memory for graphics and a configuration of a graphic display apparatus using the special purpose memory. The special purpose memory for graphics according to the present invention comprises a memory cell for holding intensity information (RGB) and window information about each pixel therein, an XY coordinate converter for converting XY coordinates of a pixel to be written to a memory address, an intensity blending processor, and hidden-surface removal and window comparators, all of which are formed on the same chip.
摘要翻译： 本发明涉及一种用于执行隐藏表面去除和颜色混合的三维图形显示装置，特别涉及用于图形的专用存储器和使用专用存储器的图形显示装置的配置的配置。 根据本发明的用于图形的专用存储器包括用于保持强度信息（RGB）和关于其每个像素的窗口信息的存储单元，用于将要写入的像素的XY坐标转换为存储器地址的XY坐标转换器， 强度混合处理器和隐藏表面去除和窗口比较器，它们都形成在同一个芯片上。
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公开(公告)号：US20060203000A1
公开(公告)日：2006-09-14
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
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公开(公告)号：US07019751B2
公开(公告)日：2006-03-28
申请号：US10636769
申请日：2003-08-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，并且缓冲装置用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US5940087A
公开(公告)日：1999-08-17
申请号：US739457
申请日：1996-10-29
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
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公开(公告)号：US06377267B1
公开(公告)日：2002-04-23
申请号：US09593496
申请日：2000-06-14
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F1300
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US06222563B1
公开(公告)日：2001-04-24
申请号：US09327355
申请日：1999-06-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F15167
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US06704019B2
公开(公告)日：2004-03-09
申请号：US10123136
申请日：2002-04-17
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G539
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US5706034A
公开(公告)日：1998-01-06
申请号：US358988
申请日：1994-12-19
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
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公开(公告)号：US07602389B2
公开(公告)日：2009-10-13
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06T15/30
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
摘要翻译： 一种数据处理系统，包括：存储器控制器; 以及连接到所述存储器控制器的存储器; 其中所述存储器控制器包括一个渲染电路，从而根据在CPU中处理程序后提供的图形数据执行一个生成显示数据的渲染命令，并将所述显示数据存储在所述存储器中。
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