公开(公告)号：US20080296729A1

公开(公告)日：2008-12-04

申请号：US12130096

申请日：2008-05-30

申请人： Ryo KUBOTA ,  Nobutaka Nagai ,  Satoshi Kura

发明人： Ryo KUBOTA ,  Nobutaka Nagai ,  Satoshi Kura

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91

摘要： A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

摘要翻译： 半导体器件通过在第一绝缘膜和覆盖在半导体衬底上的绝缘夹层延伸形成孔，通过对绝缘中间层的一部分特定的孔的内壁进行侧蚀， 从而形成具有从边缘向孔的中心突出的第一绝缘膜的结构; 在所述第一绝缘膜的上表面，侧面和背面延伸并在所述孔的内壁和底面上方形成下电极膜; 在孔中填充保护膜; 在第一绝缘膜的顶表面和侧面上分别去掉下电极膜; 去除保护膜; 并在孔中形成圆柱形电容器。

公开(公告)号：US08748282B2

公开(公告)日：2014-06-10

申请号：US13169626

申请日：2011-06-27

申请人： Ryo Kubota ,  Nobutaka Nagai ,  Satoshi Kura

发明人： Ryo Kubota ,  Nobutaka Nagai ,  Satoshi Kura

IPC分类号： H01L29/72

CPC分类号： H01L28/91

摘要： A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

摘要翻译： 半导体器件通过在第一绝缘膜和覆盖在半导体衬底上的绝缘夹层延伸形成孔，通过对绝缘中间层的一部分特定的孔的内壁进行侧蚀， 从而形成具有从边缘向孔的中心突出的第一绝缘膜的结构; 在所述第一绝缘膜的上表面，侧面和背面延伸并在所述孔的内壁和底面上方形成下电极膜; 在孔中填充保护膜; 在第一绝缘膜的顶表面和侧面上分别去掉下电极膜; 去除保护膜; 并在孔中形成圆柱形电容器。

公开(公告)号：US07985997B2

公开(公告)日：2011-07-26

申请号：US12130096

申请日：2008-05-30

申请人： Ryo Kubota ,  Nobutaka Nagai ,  Satoshi Kura

发明人： Ryo Kubota ,  Nobutaka Nagai ,  Satoshi Kura

IPC分类号： H01L29/72

CPC分类号： H01L28/91

摘要： A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

摘要翻译： 半导体器件通过在第一绝缘膜和覆盖在半导体衬底上的绝缘夹层延伸形成孔，通过对绝缘中间层的一部分特定的孔的内壁进行侧蚀， 从而形成具有从边缘向孔的中心突出的第一绝缘膜的结构; 在所述第一绝缘膜的上表面，侧面和背面延伸并在所述孔的内壁和底面上方形成下电极膜; 在孔中填充保护膜; 在第一绝缘膜的顶表面和侧面上分别去掉下电极膜; 去除保护膜; 并在孔中形成圆柱形电容器。

公开(公告)号：US20060231878A1

公开(公告)日：2006-10-19

申请号：US11408735

申请日：2006-04-17

申请人： Iwao Shirakawa ,  Nobutaka Nagai ,  Ryo Kubota

发明人： Iwao Shirakawa ,  Nobutaka Nagai ,  Ryo Kubota

IPC分类号： H01L29/94

CPC分类号： H01L27/10894

摘要： The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor 116 formed on the semiconductor substrate 102, including a structure composed of a lower electrode 118, a capacitive film 120 and an upper electrode 122, which are stacked in this sequence; an extracting unit 124 of the upper electrode 122 of the capacitor 116; and a contact 108c formed below the extracting unit 124, and providing an electrical coupling between the extracting unit 124 and an underlying interconnect such as an impurity-diffused region 103 and the like.

摘要翻译： 半导体器件100包括：半导体衬底102; 形成在半导体衬底102上的电容器116，包括以下顺序堆叠的由下电极118，电容膜120和上电极122构成的结构; 电容器116的上电极122的提取单元124; 以及形成在提取单元124下方的触点108c，并且在提取单元124和诸如杂质扩散区域103等的下层互连之间提供电耦合。

公开(公告)号：US5214316A

公开(公告)日：1993-05-25

申请号：US869747

申请日：1992-04-16

申请人： Nobutaka Nagai

发明人： Nobutaka Nagai

IPC分类号： H03K17/22

CPC分类号： H03K17/22 ,  H03K17/223

摘要： A power-on reset circuit device has a first power-on reset circuit which outputs a first reset signal, when an external power supply voltage reaches a first reference voltage, for resetting a DC-DC converter for producing a plurality of internal power supply voltages; a second power-on reset circuit which outputs a second reset signal, when the internal power supply voltage produced by the DC-DC converter reaches a second reference voltage, for resetting an internal circuit; and transistor switches for respectively inactivating the first power-on reset circuit and fixing the level of the first reset signal in response to the second reset signal. Power consumed by the power-on reset circuit device can be kept low because, in response to the second reset signal, the first power-on reset circuit is inactivated by the second power-on reset circuit. The power-on reset circuit device can be formed by a small number of circuit components required.

摘要翻译： 上电复位电路装置具有：第一上电复位电路，当外部电源电压达到第一基准电压时，输出第一复位信号，用于复位用于产生多个内部电源电压的DC-DC转换器 ; 当所述DC-DC转换器产生的内部电源电压达到第二参考电压时，输出第二复位信号的第二上电复位电路，用于复位内部电路; 以及用于分别使第一上电复位电路失活并且响应于第二复位信号固定第一复位信号的电平的晶体管开关。 上电复位电路器件消耗的功率可以保持较低，因为响应于第二复位信号，第二上电复位电路由第二上电复位电路失效。 上电复位电路器件可以由少数需要的电路元件形成。

公开(公告)号：US6020607A

公开(公告)日：2000-02-01

申请号：US603261

申请日：1996-02-20

申请人： Nobutaka Nagai

发明人： Nobutaka Nagai

IPC分类号： H01L21/337 ,  H01L29/10 ,  H01L29/808 ,  H01L29/72

CPC分类号： H01L29/66901 ,  H01L29/1066 ,  H01L29/808

摘要： An N.sup.- type epitaxial layer is formed on a P type semiconductor substrate, and a P.sup.+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N.sup.- type epitaxial layer to define a device forming region in the N.sup.- type epitaxial layer. An N.sup.+ type source diffusion layer and an N.sup.+ type drain diffusion layer are formed on the N.sup.- type epitaxial layer in the device forming region, apart from each other in one direction. A plurality of P.sup.+ type gate diffusion layers are formed between the N.sup.+ type source diffusion layer and N.sup.+ type drain diffusion layer, apart from one another in a direction perpendicular to the one direction. Channel regions for controlling the source-drain current are formed between the P.sup.+ type insulative isolating layer and the gate diffusion layer and between adjoining gate diffusion layers.

摘要翻译： 在P型半导体衬底上形成N型外延层，并且形成P +型绝缘隔离层，以从N型外延层的表面到达半导体衬底，以在N型外延层中形成器件形成区域 型外延层。 在器件形成区域的N型外延层上，在一个方向上彼此分开地形成N +型源极扩散层和N +型漏极扩散层。 在N +型源极扩散层和N +型漏极扩散层之间沿与该一个方向垂直的方向彼此分开形成多个P +型栅极扩散层。 用于控制源极 - 漏极电流的沟道区域形成在P +型绝缘隔离层和栅极扩散层之间以及相邻的栅极扩散层之间。

公开(公告)号：US5716868A

公开(公告)日：1998-02-10

申请号：US361665

申请日：1994-12-22

申请人： Nobutaka Nagai

发明人： Nobutaka Nagai

IPC分类号： H01L21/76 ,  H01L21/763

CPC分类号： H01L21/763

摘要： A method for forming a semiconductor device that can reduces the in size or height of a step generated near the mouth of a trench as compared with steps formed according to conventional methods. A semiconductor substrate is selectively removed to produce a trench therein. Next, the trench is filled with polysilicon. A top end of the polysilicon is lower than a surface of the substrate and a hollow space is produced at the top end of the trench. Then, a silicon filler is selectively formed on the top end of the polysilicon in the trench by crystal growth. A top end of the filler is substantially on the same level with the surface of the substrate. The top end of the filler is preferably higher than the surface of the substrate by -0.1 .mu.m to +0.2 .mu.m.

摘要翻译： 与根据常规方法形成的步骤相比，可以减小在沟槽口附近产生的台阶的尺寸或高度的半导体器件的形成方法。 选择性地去除半导体衬底以在其中产生沟槽。 接下来，沟槽被多晶硅填充。 多晶硅的顶端低于衬底的表面，并且在沟槽的顶端产生中空空间。 然后，通过晶体生长在沟槽中的多晶硅的顶端上选择性地形成硅填料。 填料的顶端基本上与基材表面相同的水平。 填料的顶端优选高于基材表面-0.1μm至+0.2μm。

公开(公告)号：US06177714B1

公开(公告)日：2001-01-23

申请号：US09023185

申请日：1998-02-13

申请人： Nobutaka Nagai

发明人： Nobutaka Nagai

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a laser beam make-link programmable semiconductor device, a pair of conductor strips are formed in the same level plane on a lower level insulator film formed on a semiconductor substrate, and are separated from each other in such a manner that opposing ends of the pair of conductor strips are separated by a predetermined distance smaller than a film thickness of the upper level insulator film. An upper level insulator film substantially transparent to a laser beam, is formed on the conductor strips. With this arrangement, even if a trimming laser beam has a small energy, the laser beam permeates through the upper level insulator film to reach and melt the opposing ends of the pair of conductor strips, with the result that the opposing ends of the pair of conductor strips are short-circuited.

摘要翻译： 在激光束制造链路可编程半导体器件中，在形成在半导体衬底上的下层绝缘膜上的同一电平平面上形成一对导体条，并以彼此相对的端部彼此分离 一对导体条被隔开比上层绝缘膜的膜厚小的预定距离。 在导体条上形成对激光束基本上透明的上层绝缘膜。 利用这种布置，即使修整激光束具有较小的能量，激光束也透过上层绝缘膜，以达到并熔化该对导体条的相对端，结果是一对 导线短路。

公开(公告)号：US5329177A

公开(公告)日：1994-07-12

申请号：US51566

申请日：1993-04-26

申请人： Nobutaka Nagai

发明人： Nobutaka Nagai

IPC分类号： H03K17/687 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/20

CPC分类号： H03K17/162 ,  H03K19/00361

摘要： The invention provides an output circuit in a semiconductor integrated circuit which comprises an input terminal for receiving input signals controlling output circuits, an output terminal for delivering output signals driving a load device being connected to the output terminal, high and low voltage supply lines for supplying high and low voltage driving the output circuit, a first current mirror circuit on its output stage including a single transistor being connected between the high voltage supply line and the output terminal, a second current mirror circuit on its output stage including a single transistor being connected between the low voltage supply line and the output terminal, a first logic circuit being connected between the input terminal and the first current mirror circuit for receiving input signals from the input terminal for a subsequent controlling of the first current mirror circuit, and a second logic circuit being connected between the input terminal and the second current mirror circuit for receiving input signals from the input terminal for a subsequent controlling of the second current mirror circuit.

摘要翻译： 本发明提供一种半导体集成电路中的输出电路，其包括用于接收控制输出电路的输入信号的输入端子，用于传送驱动连接到输出端子的负载装置的输出信号的输出端子，用于供应的高电压和低电压电源线 高电压和低电压驱动输出电路，其输出级上包括连接在高电压电源线和输出端之间的单个晶体管的第一电流镜电路，在其输出级上包括单个晶体管的第二电流镜电路被连接 在所述低电压电源线和所述输出端子之间，连接在所述输入端子和所述第一电流镜电路之间的第一逻辑电路，用于接收来自所述输入端子的输入信号以用于所述第一电流镜像电路的后续控制;以及第二逻辑电路 电路连接在输入端子和第二端子之间 电流镜电路，用于接收来自输入端的输入信号，用于随后控制第二电流镜电路。