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1.发明授权公开(公告)号：US09469916B2
公开(公告)日：2016-10-18
申请号：US14122042
申请日：2012-05-16
CPC分类号： C30B11/006 , C30B11/00 , C30B27/00 , C30B29/42
摘要： A method of producing a GaAs single crystal having high carrier concentration and high crystallinity and to provide a GaAs single crystal wafer using such a GaAs single crystal. In the method of producing a GaAs single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a Si material, a GaAs material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a GaAs single crystal.
摘要翻译： 一种制造具有高载流子浓度和高结晶度的GaAs单晶的方法，并且使用这种GaAs单晶来提供GaAs单晶晶片。 在制造GaAs单晶的方法中，使用接收晶种的坩埚，Si材料，作为杂质的GaAs材料，固体二氧化硅和氧化硼材料进行垂直舟形法，由此生长GaAs 单晶。
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公开(公告)号：US20140205527A1
公开(公告)日：2014-07-24
申请号：US14122042
申请日：2012-05-16
CPC分类号： C30B11/006 , C30B11/00 , C30B27/00 , C30B29/42
摘要： A method of producing a GaAs single crystal having high carrier concentration and high crystallinity and to provide a GaAs single crystal wafer using such a GaAs single crystal. In the method of producing a GaAs single crystal, a vertical boat method is performed with a crucible receiving a seed crystal, a Si material, a GaAs material serving as an impurity, solid silicon dioxide, and a boron oxide material, thereby growing a GaAs single crystal.
摘要翻译： 一种制造具有高载流子浓度和高结晶度的GaAs单晶的方法，并且使用这种GaAs单晶来提供GaAs单晶晶片。 在制造GaAs单晶的方法中，使用接收晶种的坩埚，Si材料，作为杂质的GaAs材料，固体二氧化硅和氧化硼材料进行垂直舟形法，由此生长GaAs 单晶。
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公开(公告)号：US07990756B2
公开(公告)日：2011-08-02
申请号：US12211501
申请日：2008-09-16
申请人： Ryoichi Nakamura
发明人： Ryoichi Nakamura
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , H01L27/11 , H01L27/1104
摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.
摘要翻译： 本文公开了一种半导体存储器件，其包括多个存储单元，其包括第一和第二反相器，每个具有第一和第二驱动晶体管以及第一和第二负载晶体管，并且包括第一和第二存储器节点以及第一和第二转移晶体管。 第一和第二传输晶体管分别连接到第一和存储器节点中的每一个。 存储单元经由第一和第二传输晶体管分别连接到位线和互补位线，其中施加到位线和互补位线的电源电压低于施加到负载晶体管的电源电压，并且至少 第一驱动晶体管，第二驱动晶体管，第一负载晶体管和第二负载晶体管的栅极绝缘膜的存储器节点侧端部的厚度大于另一部分的栅极绝缘膜的厚度。
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4.发明授权
公开(公告)号：US5193033A
公开(公告)日：1993-03-09
申请号：US794784
申请日：1991-11-18
IPC分类号： G11B5/41 , G11B15/087 , G11B27/36
CPC分类号： G11B27/36 , G11B15/087 , G11B5/41
摘要： A magnetic recording/reproducing apparatus incorporating a clogging detector includes comparator for comparing with a predetermined value an absolute value of signals which are produced by reproducing recorded signals immediately after recording. Clogging signals may be supplied to cleaner for cleaning heads when the absolute value is less than the predetermined value.
摘要翻译： 包含堵塞检测器的磁记录/再现装置包括比较器，用于与记录之后立即重现记录信号产生的信号的绝对值与预定值进行比较。 当绝对值小于预定值时，可将堵塞信号提供给用于清洁头的清洁器。
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公开(公告)号：US07985197B2
公开(公告)日：2011-07-26
申请号：US12123005
申请日：2008-05-19
申请人： Masanori Maeda , Hidenori Takushima , Teruo Okano , Masayuki Yamato , Hiroshi Iseki , Ryoichi Nakamura , Takamasa Onuki , Masato Kanzaki , Takashi Suzuki , Shigeru Nagai
发明人： Masanori Maeda , Hidenori Takushima , Teruo Okano , Masayuki Yamato , Hiroshi Iseki , Ryoichi Nakamura , Takamasa Onuki , Masato Kanzaki , Takashi Suzuki , Shigeru Nagai
IPC分类号： A61M31/00
CPC分类号： A61B17/3468
摘要： A therapeutic-substance carrying/administering appliance includes a cylindrical outer sheath; a slide member installed in the cylindrical outer sheath to be slidable therein; and a sheet supporting member, connected to a distal end of the slide member and made of a resilient material, for supporting a sheet-shaped therapeutic substance. The sheet supporting member is held in a flat unrolled shape in a free state in which the sheet supporting member projects outwardly from a distal end of the cylindrical outer sheath. When the sheet supporting member is in the free state, sliding the slide member in a retracting direction causes the sheet supporting member to contact the distal end of the cylindrical outer sheath, and subsequently further moving the slide member in the retracting direction causes the sheet supporting member to be retracted into the cylindrical outer sheath while being deformed into a tubular shape.
摘要翻译： 治疗物质携带/给药器具包括圆柱形外护套; 安装在所述圆筒形外护套中的可在其中滑动的滑动构件; 以及片材支撑构件，其连接到滑动构件的远端并由弹性材料制成，用于支撑片状治疗物质。 片材支撑构件在自由状态下保持为平坦的未卷曲形状，其中片材支撑构件从圆柱形外护套的远端向外突出。 当片材支撑构件处于自由状态时，滑动构件沿缩回方向使片材支撑构件接触圆柱形外护套的远端，并且随后在缩回方向上进一步移动滑动构件使得片材支撑 构件在变形为管状时被缩回到圆柱形外护套中。
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6.发明授权Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same 有权具有n +（p）掺杂n型栅极的混合半导体器件及其制造方法公开(公告)号：US07057243B2
公开(公告)日：2006-06-06
申请号：US10648883
申请日：2003-08-27
申请人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
发明人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
摘要翻译： 在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。 具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。 具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。
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公开(公告)号：US20090080236A1
公开(公告)日：2009-03-26
申请号：US12211501
申请日：2008-09-16
申请人： Ryoichi Nakamura
发明人： Ryoichi Nakamura
IPC分类号： G11C11/00 , G11C11/34 , H01L21/00 , H01L21/336
CPC分类号： G11C11/417 , H01L27/11 , H01L27/1104
摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.
摘要翻译： 本文公开了一种半导体存储器件，其包括多个存储单元，其包括第一和第二反相器，每个具有第一和第二驱动晶体管以及第一和第二负载晶体管，并且包括第一和第二存储器节点以及第一和第二转移晶体管。 第一和第二传输晶体管分别连接到第一和存储器节点中的每一个。 存储单元经由第一和第二传输晶体管分别连接到位线和互补位线，其中施加到位线和互补位线的电源电压低于施加到负载晶体管的电源电压，并且至少 第一驱动晶体管，第二驱动晶体管，第一负载晶体管和第二负载晶体管的栅极绝缘膜的存储器节点侧端部的厚度大于另一部分的栅极绝缘膜的厚度。
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公开(公告)号：US07414291B2
公开(公告)日：2008-08-19
申请号：US11099511
申请日：2005-04-06
IPC分类号： H01L29/72
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76805 , H01L21/76814 , H01L29/78
摘要： A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.
摘要翻译： 一种方法包括以下步骤：将硼注入到硅衬底的表面区域中以形成p + +扩散区; 将铟注入到扩散区域的表面中以形成铟注入层; 在铟注入层上形成接触金属层; 并且在包含铟注入层的硅衬底中的硅与金属在接触金属层中反应以形成硅化钛层。
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公开(公告)号：US20050230712A1
公开(公告)日：2005-10-20
申请号：US11099511
申请日：2005-04-06
IPC分类号： H01L21/28 , H01L21/26 , H01L21/265 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/74 , H01L21/768 , H01L23/52 , H01L27/10 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76805 , H01L21/76814 , H01L29/78
摘要： A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.
摘要翻译： 一种方法包括以下步骤：将硼注入到硅衬底的表面区域中以形成p + +扩散区; 将铟注入到扩散区域的表面中以形成铟注入层; 在铟注入层上形成接触金属层; 并且在包含铟注入层的硅衬底中的硅与金属在接触金属层中反应以形成硅化钛层。
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10.发明授权公开(公告)号：US06653230B2
公开(公告)日：2003-11-25
申请号：US10119023
申请日：2002-04-10
申请人： Ryoichi Nakamura
发明人： Ryoichi Nakamura
IPC分类号： H01L214763
CPC分类号： H01L27/10855 , H01L27/10811 , H01L27/10888 , H01L28/84 , H01L28/91
摘要： It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. Gate electrodes are formed on a p-well in such a manner that the gate electrode interval in storage electrode forming portions is longer than that in a bit contact plug forming portion, and sidewalls are then formed. An SiO2 film is deposited, storage electrode forming holes and a bit contact plug forming holes are formed therein, and then a polysilicon film is deposited. Another SiO2 film is deposited on the polysilicon film and etched back. Then, the polysilicon film is etched back. After etching of the SiO2 films, capacitor insulating films and counter electrodes are formed and a bit line is also formed.
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