公开(公告)号：US08455269B2

公开(公告)日：2013-06-04

申请号：US12376199

申请日：2006-08-04

申请人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

发明人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L23/345 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.

摘要翻译： 在双极型半导体器件中，在通态正向偏压工作时，从碳化硅单晶衬底的表面生长的碳化硅外延膜中电子和空穴复合; 在碳化硅双极半导体器件中增加的导通状态正向电压通过收缩通过接通状态正向偏置操作而扩大的堆垛层错的区域来恢复。 在本发明的方法中，通过接通状态的正向偏压操作来增加堆垛层错扩大区域和导通状态正向电压的双极性半导体器件在高于350℃的温度下被加热。

公开(公告)号：US08367510B2

公开(公告)日：2013-02-05

申请号：US12067028

申请日：2006-09-01

申请人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiro Nagano ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

发明人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiro Nagano ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

IPC分类号： H01L21/331

CPC分类号： H01L29/66068 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/861

摘要： In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.

摘要翻译： 在从碳化硅单晶衬底的表面生长的碳化硅外延膜内的电流通过期间电子和空穴彼此复合的双极性碳化硅半导体器件中，本文所述的目的是减少 通过电流通过而扩展的堆垛层错的核，由此抑制双极性碳化硅半导体器件的正向电压的增加。 在制造双极性碳化硅半导体器件的方法中，在最后的制造工序中，在300℃以上的温度下进行热处理。 优选地，上述热处理在电极形成之后进行，然后将所得到的双极性碳化硅半导体器件安装在封装中。

公开(公告)号：US20100084663A1

公开(公告)日：2010-04-08

申请号：US12597121

申请日：2008-04-25

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

IPC分类号： H01L29/866 ,  H01L29/24

CPC分类号： H01L29/866 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/66106

摘要： A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.

摘要翻译： 一种碳化硅齐纳二极管是具有台面结构的双极半导体器件，包括形成在其上的第一导电类型的碳化硅单晶衬底，第一导电类型的碳化硅导电层和碳化硅导电层 形成在第一导电类型的碳化硅导电层上的第二导电类型，其中在第一导电类型的碳化硅导电层与第二导电类型的碳化硅导电层之间的接合处以反偏压形成的耗尽层 导电类型不到达形成在第一导电类型的碳化硅导电层中的台面角。

公开(公告)号：US08178949B2

公开(公告)日：2012-05-15

申请号：US12525198

申请日：2008-01-31

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

IPC分类号： H01L21/331

CPC分类号： H01L29/866 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66106 ,  H01L29/8613

摘要： Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named.

摘要翻译： 双极半导体器件在齐纳电压的宽范围（例如10至500V）内非常精确地控制齐纳电压。 双极半导体器件具有台面结构，并且包括第一导电类型的碳化硅单晶衬底，第一导电类型的碳化硅导电层，第二导电类型的高掺杂层和碳化硅导电层 第二导电类型，其中基板和导电层按顺序层压。

公开(公告)号：US08154026B2

公开(公告)日：2012-04-10

申请号：US12097019

申请日：2006-12-13

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Tomonori Nakamura

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Tomonori Nakamura

IPC分类号： H01L29/15

CPC分类号： H01L29/1604 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8613

摘要： In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer.

摘要翻译： 在具有由SiC单晶衬底的表面生长的SiC外延层的具有第一导电类型的SiC漂移层和第二导电类型的SiC载流子注入层的台阶结构的SiC双极型半导体器件中，形成 防止堆垛层错及其面积的膨胀，从而防止正向电压的增加。 此外，提高了反向偏置中的耐受电压的特性。 在台面壁或台面壁和台面周边上形成正向操作降解防止层，以在空间上分离台面壁的表面与pn结界面。 在一个实施例中，正向操作降解防止层由在施加反向电压期间具有等电位的第二导电类型的碳化硅低电阻层构成。 在另一个实施方案中，正向操作降解防止层由第二导电类型的碳化硅导电层构成，并且在施加反向电压期间具有等电位的金属层形成在碳化硅导电层的表面上 。 在另一个实施方案中，正向操作降解防止层由高电阻非晶层组成。

公开(公告)号：US08093599B2

公开(公告)日：2012-01-10

申请号：US12597121

申请日：2008-04-25

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

IPC分类号： H01L29/866

CPC分类号： H01L29/866 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/66106

摘要： A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.

摘要翻译： 一种碳化硅齐纳二极管是具有台面结构的双极半导体器件，包括形成在其上的第一导电类型的碳化硅单晶衬底，第一导电类型的碳化硅导电层和碳化硅导电层 形成在第一导电类型的碳化硅导电层上的第二导电类型，其中在第一导电类型的碳化硅导电层与第二导电类型的碳化硅导电层之间的接合处以反偏压形成的耗尽层 导电类型不到达形成在第一导电类型的碳化硅导电层中的台面角。

公开(公告)号：US20090195296A1

公开(公告)日：2009-08-06

申请号：US12376199

申请日：2006-08-04

申请人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

发明人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

IPC分类号： G11C5/14 ,  H01L23/00 ,  H01L29/70 ,  H01L21/322

CPC分类号： H01L29/045 ,  H01L23/345 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.

摘要翻译： 在双极型半导体器件中，在通态正向偏压工作时，从碳化硅单晶衬底的表面生长的碳化硅外延膜中电子和空穴复合; 在碳化硅双极半导体器件中增加的导通状态正向电压通过收缩通过接通状态正向偏置操作而扩大的堆垛层错的区域来恢复。 在本发明的方法中，通过接通状态的正向偏压操作来增加堆垛层错扩大区域和导通状态正向电压的双极性半导体器件在高于350℃的温度下被加热。

公开(公告)号：US20090045413A1

公开(公告)日：2009-02-19

申请号：US12097019

申请日：2006-12-13

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Tomonori Nakamura

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Tomonori Nakamura

IPC分类号： H01L29/24

CPC分类号： H01L29/1604 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8613

摘要： In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer.

摘要翻译： 在具有由SiC单晶衬底的表面生长的SiC外延层的具有第一导电类型的SiC漂移层和第二导电类型的SiC载流子注入层的台阶结构的SiC双极型半导体器件中，形成 防止堆垛层错及其面积的膨胀，从而防止正向电压的增加。 此外，提高了反向偏置中的耐受电压的特性。 在台面壁或台面壁和台面周边上形成正向操作降解防止层，以在空间上分离台面壁的表面与pn结界面。 在一个实施例中，正向操作降解防止层由在施加反向电压期间具有等电位的第二导电类型的碳化硅低电阻层构成。 在另一个实施方案中，正向操作降解防止层由第二导电类型的碳化硅导电层构成，并且在施加反向电压期间具有等电位的金属层形成在碳化硅导电层的表面上 。 在另一个实施方案中，正向操作降解防止层由高电阻非晶层组成。

公开(公告)号：US20100032686A1

公开(公告)日：2010-02-11

申请号：US12525198

申请日：2008-01-31

申请人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

发明人： Ryosuke Ishii ,  Koji Nakayama ,  Yoshitaka Sugawara ,  Hidekazu Tsuchida

IPC分类号： H01L29/866 ,  H01L21/04

CPC分类号： H01L29/866 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66106 ,  H01L29/8613

摘要： Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named.

摘要翻译： 双极半导体器件在齐纳电压的宽范围（例如10至500V）内非常精确地控制齐纳电压。 双极半导体器件具有台面结构，并且包括第一导电类型的碳化硅单晶衬底，第一导电类型的碳化硅导电层，第二导电类型的高掺杂层和碳化硅导电层 第二导电类型，其中基板和导电层按顺序层压。

公开(公告)号：US20090317983A1

公开(公告)日：2009-12-24

申请号：US12067028

申请日：2006-09-01

申请人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiro Nagano ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

发明人： Toshiyuki Miyanagi ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiro Nagano ,  Yoshitaka Sugawara ,  Koji Nakayama ,  Ryosuke Ishii

IPC分类号： H01L21/26

CPC分类号： H01L29/66068 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/861

摘要： In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.

摘要翻译： 在从碳化硅单晶衬底的表面生长的碳化硅外延膜内的电流通过期间电子和空穴彼此复合的双极性碳化硅半导体器件中，本文所述的目的是减少 通过电流通过而扩展的堆垛层错的核，由此抑制双极性碳化硅半导体器件的正向电压的增加。 在制造双极性碳化硅半导体器件的方法中，在最后的制造工序中，在300℃以上的温度下进行热处理。 优选地，上述热处理在电极形成之后进行，然后将所得到的双极性碳化硅半导体器件安装在封装中。