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公开(公告)号：US20080168232A1
公开(公告)日：2008-07-10
申请号：US10577133
申请日：2004-11-02
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/121
摘要： A cache memory according to the present invention includes: a W flag setting unit (40) that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order; and a replace unit (39) that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
摘要翻译： 根据本发明的缓存存储器包括：W标志设置单元，其修改指示保存高速缓存的数据单元的每个高速缓存条目的访问顺序的顺序数据，以便反映实际的访问顺序; 以及替换单元（39），其基于修改的订单数据选择用于替换的高速缓存条目并替换高速缓存条目。
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公开(公告)号：US20070143548A1
公开(公告)日：2007-06-21
申请号：US10583773
申请日：2004-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。
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公开(公告)号：US07454575B2
公开(公告)日：2008-11-18
申请号：US10583773
申请日：2004-12-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译： 本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否 缓存条目已经写入。 本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置 在高速缓存条目保存未被写回的重写数据的状态下的脏标志。
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公开(公告)号：US07185176B2
公开(公告)日：2007-02-27
申请号：US10449788
申请日：2003-06-02
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
IPC分类号： G06F15/80
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3887 , G06F15/8015
摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.
摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。
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5.发明授权Cache memory and method for cache entry replacement based on modified access order 有权基于修改的访问顺序的缓存内存和缓存条目替换方法公开(公告)号：US07984243B2
公开(公告)日：2011-07-19
申请号：US10577133
申请日：2004-11-02
申请人： Hazuki Kawai , Ryuta Nakanishi , Tetsuya Tanaka , Shuji Miyasaka
发明人： Hazuki Kawai , Ryuta Nakanishi , Tetsuya Tanaka , Shuji Miyasaka
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/121
摘要： A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
摘要翻译： 根据本发明的高速缓冲存储器包括：W标志设置单元，其修改指示保存高速缓存的数据单元的每个高速缓存条目的访问顺序的顺序数据，以反映实际的访问顺序;以及替换单元，其选择高速缓存条目 根据修改的订单数据进行替换，并替换高速缓存条目。
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公开(公告)号：US09153241B2
公开(公告)日：2015-10-06
申请号：US12438996
申请日：2007-11-29
IPC分类号： H04W4/00 , G10L19/16 , G10L21/038 , H04Q11/04 , G11B20/00
CPC分类号： G10L19/167 , G10L21/038 , G11B2020/00028 , H04Q11/0428
摘要： The signal processing apparatus inserts the header information in a frame to probably be the reproduction start point by including: the first and the second coding units that code an input signal per frame; the first header inserting unit that inserts the SBR header indicating management information of the coded signal represented by a sequence of frames, in each frame at a regular interval within the coded signal; the control unit that determines a frame in which the SBR header is inserted, independent of the frames in which the first header inserting unit inserts the SBR header; and the second header inserting unit that singly inserts the SBR header in the frame determined by the control unit.
摘要翻译： 信号处理装置通过包括以下步骤将头部信息插入到可能是再现开始点的帧中：第一和第二编码单元，每帧编码输入信号; 第一标题插入单元，以编码信号内的规则间隔，插入表示由帧序列表示的编码信号的管理信息的SBR标题; 所述控制单元确定其中插入所述SBR报头的帧，与所述第一报头插入单元插入所述SBR报头的帧无关; 以及第二标题插入单元，其将SBR标题单独地插入由控制单元确定的帧中。
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公开(公告)号：US08081764B2
公开(公告)日：2011-12-20
申请号：US11993066
申请日：2006-07-11
申请人： Yosiaki Takagi , Kok seng Chong , Takeshi Norimatsu , Shuji Miyasaka , Akihisa Kawamura , Kojiro Ono
发明人： Yosiaki Takagi , Kok seng Chong , Takeshi Norimatsu , Shuji Miyasaka , Akihisa Kawamura , Kojiro Ono
IPC分类号： H04R5/00
CPC分类号： G10L19/008 , G10L19/0204
摘要： Provided is an audio decoder which can reduce an amount of arithmetic operations while suppressing occurrence of aliasing noise. The audio decoder includes: a decoder (102) and an analysis filter bank (110) which generate, from a coded down-mixed signal, the first frequency band signal (x) corresponding to a down-mixed signal (M); a channel expansion unit (130) which converts the first frequency band signal (x) generated by the analysis filter bank (110) into output signals (y) corresponding to respective audio signals of N channels, using BC information; an synthesis filter bank (140) which performs band synthesis for the output signals (y) generate by the channel expansion unit (130) and thereby converts the output signals (y) into the respective audio signals of the N channels on a time axis; and an aliasing noise detection unit (120) which detects occurrence of aliasing noise in the first frequency band signal (x). The channel expansion unit (130) further prevents the aliasing noise from being included in the output signals (y), based on information detected by the aliasing noise detection unit (120).
摘要翻译： 提供一种音频解码器，其可以在抑制混叠噪声的发生的同时减少算术运算量。 音频解码器包括：解码器（102）和分析滤波器组（110），其从编码的下变频信号产生与下混合信号（M）对应的第一频带信号（x）; 信道扩展单元，其使用BC信息将由分析滤波器组（110）生成的第一频带信号（x）转换成对应于N个信道的各个音频信号的输出信号（y）; 合成滤波器组（140），其对由所述信道扩展单元（130）生成的输出信号（y）进行频带合成，从而将输出信号（y）转换成时间轴上的N个信道的各个音频信号; 以及用于检测第一频带信号（x）中的混叠噪声的出现的混叠噪声检测单元（120）。 信道扩展单元（130）还基于混叠噪声检测单元（120）检测到的信息进一步防止混叠噪声包含在输出信号（y）中。
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公开(公告)号：US08019614B2
公开(公告)日：2011-09-13
申请号：US12065378
申请日：2006-08-31
申请人： Yoshiaki Takagi , Kok Seng Chong , Takeshi Norimatsu , Shuji Miyasaka , Akihisa Kawamura , Kojiro Ono , Tomokazu Ishikawa
发明人： Yoshiaki Takagi , Kok Seng Chong , Takeshi Norimatsu , Shuji Miyasaka , Akihisa Kawamura , Kojiro Ono , Tomokazu Ishikawa
IPC分类号： G10L19/00
CPC分类号： G10L19/26 , G10L19/008 , G10L19/0204 , H04S2420/03
摘要： A temporal processing apparatus includes: a splitter splitting an audio signal, included in the sub-band domain, into diffuse signals indicating reverberating components and direct signals indicating non-reverberating components; a downmix unit generating a downmix signal by downmixing the direct signals; BPFs respectively generating a bandpass downmix signal and bandpass diffuse signals; normalization processing units respectively generating a normalized downmix signal and normalized diffuse signals; a scale computation processing unit computing, on a predetermined time slot basis, a scale factor indicating the magnitude of energy of the normalized downmix signal with respect to energy of the normalized diffuse signals; a calculating unit generating scale diffuse signals; a HPF generating high-pass diffuse signals; an adding unit generating addition signals; and a synthesis filter bank performing synthesis filter processing on the addition signals and transforming the addition signals into the time domains.
摘要翻译： 时间处理装置包括：分离器，将包括在子带域中的音频信号分成指示混响分量的漫射信号和指示非混响分量的直接信号; 下混合单元，通过使直接信号下混合来产生降混信号; BPF分别产生带通下混信号和带通漫射信号; 归一化处理单元，分别产生归一化的下混信号和归一化扩散信号; 比例计算处理单元在预定时隙的基础上计算指示归一化的下混信号相对于归一化扩散信号的能量的能量的大小的比例因子; 计算单元，生成缩放漫射信号; HPF产生高通漫反射信号; 添加单元生成附加信号; 以及合成滤波器组，对加法信号执行合成滤波处理，并将加法信号转换成时域。
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9.发明申请公开(公告)号：US20070239463A1
公开(公告)日：2007-10-11
申请号：US11806971
申请日：2007-06-05
IPC分类号： G10L19/00
摘要： A decoding device (30a) comprises a narrow-band decoding unit (31) operable to reproduce a PCM signal (P1) from a narrow-band bit stream included in a wide-band bit stream (S0), a wide-band decoding unit (32) operable to reproduce a PCM signal (P2) having a frequency band which is wider than that of the PCM signal (P1) reproduced by the narrow-band decoding unit (31) from the narrow-band bit stream and a band expanding bit stream included in the wide band bit stream (S0) and a selecting unit (34) operable to select either the PCM signal (P1) reproduced by the narrow-band decoding unit (31) or the PCM signal (P2) reproduced by the wide-band decoding unit (32), and to output the selected sound digital signal.
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公开(公告)号：US07243061B2
公开(公告)日：2007-07-10
申请号：US10954589
申请日：2004-10-01
IPC分类号： G10L19/02
CPC分类号： G10L19/032 , G10L19/0212 , G10L19/038
摘要： With respect to audio signal coding and decoding apparatuses, there is provided a coding apparatus that enables a decoding apparatus to reproduce an audio signal even through it does not use all of data from the coding apparatus, and a decoding apparatus corresponding to the coding apparatus. A quantization unit constituting a coding apparatus includes a first sub-quantization unit comprising sub-quantization units for low-band, intermediate-band, and high-band; a second sub-quantization unit for quantizing quantization errors from the first sub-quantization unit; and a third sub-quantization unit for quantizing quantization errors which have been processed by the first sub-quantization unit and the second sub-quantization unit.
摘要翻译： 对于音频信号编码和解码装置，提供了一种编码装置，即使通过编码装置不使用全部数据，能够使解码装置再现音频信号，也可以使用与编码装置对应的解码装置。 构成编码装置的量化单元包括：第一子量化单元，包括用于低频带，中频带和高频带的子量化单元; 第二子量化单元，用于量化来自第一子量化单元的量化误差; 以及用于量化由第一子量化单元和第二子量化单元处理的量化误差的第三子量化单元。
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