公开(公告)号：US07185176B2

公开(公告)日：2007-02-27

申请号：US10449788

申请日：2003-06-02

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

IPC分类号： G06F15/80

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。

公开(公告)号：US20080046687A1

公开(公告)日：2008-02-21

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F15/80

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US07594099B2

公开(公告)日：2009-09-22

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/305

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1， 并非所有向量条件标志都为零。 然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

公开(公告)号：US20080046690A1

公开(公告)日：2008-02-21

申请号：US11896370

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US20080046688A1

公开(公告)日：2008-02-21

申请号：US11896369

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F15/80 ,  G06F9/315

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US07281117B2

公开(公告)日：2007-10-09

申请号：US10668358

申请日：2003-09-24

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F9/318

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US20080209407A1

公开(公告)日：2008-08-28

申请号：US12109707

申请日：2008-04-25

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F9/45

CPC分类号： G06F9/30072 ,  G06F8/447 ,  G06F9/325

摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指​​令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。

公开(公告)号：US07380112B2

公开(公告)日：2008-05-27

申请号：US10805381

申请日：2004-03-22

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30072 ,  G06F8/447 ,  G06F9/325

摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指​​令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。

公开(公告)号：US20050144420A1

公开(公告)日：2005-06-30

申请号：US10995148

申请日：2004-11-24

申请人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

发明人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

IPC分类号： G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

CPC分类号： G06F9/342 ,  G06F8/4442 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0888 ,  G06F2212/6028

摘要： The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.

摘要翻译： 能够有效地使用高速缓冲存储器的数据处理装置包括：高速缓存存储器28和存储由物理地址指定的每个区域中的指令或数据的存储器30; 输出包括表示规定处理的物理地址和处理确定数据的逻辑地址的算术处理单元22，获得与包含在逻辑地址中的物理地址相对应的指令或数据，并执行指令; 地址转换单元26，其将由运算处理单元22输出的逻辑地址转换成物理地址。 数据处理装置读取存储在高速缓冲存储器28和存储器30中由物理地址指定的区域中的指令或数据，并根据处理确定数据执行规定的处理。

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。