公开(公告)号：US07185176B2

公开(公告)日：2007-02-27

申请号：US10449788

申请日：2003-06-02

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

IPC分类号： G06F15/80

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。

公开(公告)号：US07594099B2

公开(公告)日：2009-09-22

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/305

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1， 并非所有向量条件标志都为零。 然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

公开(公告)号：US20080046704A1

公开(公告)日：2008-02-21

申请号：US11896371

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki OKabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki OKabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/38

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US20080046687A1

公开(公告)日：2008-02-21

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F15/80

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US20080046688A1

公开(公告)日：2008-02-21

申请号：US11896369

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F15/80 ,  G06F9/315

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US07281117B2

公开(公告)日：2007-10-09

申请号：US10668358

申请日：2003-09-24

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F9/318

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

摘要翻译： 根据本发明的处理器包括解码单元20，操作单元40等。 当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件 当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。 然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

公开(公告)号：US20080046690A1

公开(公告)日：2008-02-21

申请号：US11896370

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。

公开(公告)号：US20070186048A1

公开(公告)日：2007-08-09

申请号：US10599170

申请日：2005-03-16

申请人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Tokuzo Kiyohara

发明人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Tokuzo Kiyohara

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line data, from the memory to the cache memory; and a touch unit 415 which sets the predicted line address to the cache entry, as a tag, and validates the valid flag, without loading data from the memory into the cache memory

摘要翻译： 本发明的高速缓冲存储器包括：预测单元39，其基于从存储器输出的存储器访问的进度，预测下一个预取的行地址。 预测单元39包括：预取单元414，其将预测行数据的数据从存储器预取到高速缓冲存储器; 以及触摸单元415，其将预测线路地址设置为高速缓存条目作为标签，并且验证有效标志，而不将数据从存储器加载到高速缓冲存储器

公开(公告)号：US20080215858A1

公开(公告)日：2008-09-04

申请号：US12110539

申请日：2008-04-28

申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。