公开(公告)号：US20120300533A1

公开(公告)日：2012-11-29

申请号：US13568834

申请日：2012-08-07

申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

IPC分类号： G11C11/00 ,  H01L27/26 ,  H01L47/00

CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

摘要翻译： 提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导​​体和半导体结二极管。 半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。 此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。 提供了许多其他方面。

公开(公告)号：US08243509B2

公开(公告)日：2012-08-14

申请号：US13074509

申请日：2011-03-29

申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

IPC分类号： G11C11/36 ,  G11C11/34 ,  G11C11/00

CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.

摘要翻译： 描述非易失性存储单元，存储单元包括半导体二极管。 构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。 编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。 在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。 电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。 描述了产生有利的未编程缺陷密度的制造技术。 本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

公开(公告)号：US20110176352A1

公开(公告)日：2011-07-21

申请号：US13074509

申请日：2011-03-29

申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

IPC分类号： G11C11/36

CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.

摘要翻译： 描述非易失性存储单元，存储单元包括半导体二极管。 构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。 编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。 在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。 电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。 描述了产生有利的未编程缺陷密度的制造技术。 本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

公开(公告)号：US07888205B2

公开(公告)日：2011-02-15

申请号：US12659480

申请日：2010-03-10

申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11578

摘要： Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

摘要翻译： PMOS或NMOS薄膜晶体管的尺寸缩小受掺杂剂扩散的限制。 在这些器件中，未掺杂或轻掺杂的沟道区被插入在重掺杂的源极和漏极区之间。 当器件以非常短的栅极长度构建时，源极和漏极掺杂物将扩散到沟道中，从而潜在地短路并破坏器件。 描述了一组创新，其可以以各种组合使用，以在制造PMOS或NMOS多晶薄膜晶体管期间最小化掺杂剂扩散，导致高度可缩放的薄膜晶体管。 该晶体管特别适用于堆叠器件级的单片三维阵列。

公开(公告)号：US08482973B2

公开(公告)日：2013-07-09

申请号：US13568834

申请日：2012-08-07

申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

IPC分类号： G11C11/36 ,  G11C11/34 ,  G11C11/00

CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

摘要翻译： 提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导​​体和半导体结二极管。 半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。 此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。 提供了许多其他方面。

公开(公告)号：US20070007577A1

公开(公告)日：2007-01-11

申请号：US11175688

申请日：2005-07-06

申请人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

发明人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.

摘要翻译： 提供了包括至少一个存储单元的集成电路。 这样的存储单元又包括晶体管和电容器。 晶体管包括源极，漏极和栅极。 此外，电容器包括阱和栅极。 晶体管的栅极保持与电容器的栅极通信。 在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。 在这样的实施例中，晶体管的阱邻接电容器的阱。 在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

公开(公告)号：US08883589B2

公开(公告)日：2014-11-11

申请号：US12892633

申请日：2010-09-28

申请人： Xiying Costa ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Brian Le ,  Yung-Tin Chen

发明人： Xiying Costa ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Brian Le ,  Yung-Tin Chen

IPC分类号： H01L21/8234 ,  H01L27/24 ,  H01L27/102 ,  H01L45/00

CPC分类号： H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1675

摘要： A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.

摘要翻译： 提供一种形成存储单元的方法，所述方法包括形成二极管，该二极管包括具有第一导电类型的第一区域，对二极管进行反掺杂以将第一区域改变为第二导电类型，以及形成串联耦合的存储元件 与二极管。 还提供其他方面。

公开(公告)号：US08520424B2

公开(公告)日：2013-08-27

申请号：US13157204

申请日：2011-06-09

申请人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S. Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

发明人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S. Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：US08289749B2

公开(公告)日：2012-10-16

申请号：US12642191

申请日：2009-12-18

申请人： Xiying Chen ,  Abhijit Bandyopadhyay ,  Brian Le ,  Roy Scheuerlein ,  Li Xiao

发明人： Xiying Chen ,  Abhijit Bandyopadhyay ,  Brian Le ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/34

摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.

摘要翻译： 本文描述了用于形成可逆电阻率开关元件的方法和系统。 形成是指降低可逆电阻率开关元件的电阻，并且通常被理解为指第一次降低电阻。 在形成可逆电阻率开关元件之前，它可能处于高电阻状态。 施加第一电压以部分地形成可逆电阻率开关元件。 第一电压具有第一极性。 部分形成可逆电阻率开关元件降低可逆电阻率开关元件的电阻。 然后将具有与第一相反极性的第二电压施加到可逆电阻率开关元件。 第二电压的施加可以进一步降低可逆电阻率开关元件的电阻。 因此，可以将第二电压视为完成可逆电阻率开关元件的形成。

公开(公告)号：US08207064B2

公开(公告)日：2012-06-26

申请号：US12562079

申请日：2009-09-17

申请人： Abhijit Bandyopadhyay ,  Kun Hou ,  Steven Maxwell

发明人： Abhijit Bandyopadhyay ,  Kun Hou ,  Steven Maxwell

IPC分类号： H01L21/44

CPC分类号： H01L29/868 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/165 ,  H01L29/452 ,  H01L29/456 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

摘要翻译： 半导体p-i-n二极管及其形成方法在此描述。 在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。 在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。