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1.发明授权Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device 有权NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成方法公开(公告)号：US08658499B2
公开(公告)日：2014-02-25
申请号：US13544328
申请日：2012-07-09
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译： 单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。 该串还包括阻挡介电层，电荷存储区和隧道电介质。 第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。
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公开(公告)号：US08148230B2
公开(公告)日：2012-04-03
申请号：US12656306
申请日：2010-01-25
申请人： Vance Dunton , Raghuveer S. Makala , Michael Chan
发明人： Vance Dunton , Raghuveer S. Makala , Michael Chan
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L21/32134 , H01L27/1021 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.
摘要翻译： 制造半导体器件的方法包括提供包含多个开口的绝缘层，在多个开口中形成第一导电类型半导体层，在多个开口中的第一导电类型半导体层上形成第二导电类型半导体层 并且使用第一导电类型半导体层的上表面作为停止来选择性地蚀刻第二导电类型半导体层，以在多个开口中形成凹部。
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3.发明申请公开(公告)号：US20080292531A1
公开(公告)日：2008-11-27
申请号：US11874543
申请日：2007-10-18
CPC分类号： C01B31/00 , B82Y30/00 , B82Y40/00 , C01B32/00 , C01B32/174 , C01B32/176 , C01B2202/06 , D01F9/12 , Y10S977/752 , Y10S977/842 , Y10S977/847
摘要： A method of cutting, thinning, welding and chemically functionalizing multiwalled carbon nanotubes (CNTs) with carboxyl and allyl moieties, and altering the electrical properties of the CNT films by applying high current densities combined with air-exposure is developed and demonstrated. Such welded high-conductance CNT networks of functionalized CNTs could be useful for device and sensor applications, and may serve as high mechanical toughness mat fillers that are amenable to integration with nanocomposite matrices.
摘要翻译： 开发并展示了通过与空气暴露结合使用高电流密度来切割，变薄，焊接和化学官能化具有羧基和烯丙基部分的多壁碳纳米管（CNT）以及改变CNT膜的电性能的方法。 功能化CNT的这种焊接高电导CNT网络可用于器件和传感器应用，并且可以用作适于与纳米复合材料基体结合的高机械韧性垫填料。
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4.发明授权公开(公告)号：US08758717B2
公开(公告)日：2014-06-24
申请号：US11874543
申请日：2007-10-18
CPC分类号： C01B31/00 , B82Y30/00 , B82Y40/00 , C01B32/00 , C01B32/174 , C01B32/176 , C01B2202/06 , D01F9/12 , Y10S977/752 , Y10S977/842 , Y10S977/847
摘要： A method of cutting, thinning, welding and chemically functionalizing multiwalled carbon nanotubes (CNTs) with carboxyl and allyl moieties, and altering the electrical properties of the CNT films by applying high current densities combined with air-exposure is developed and demonstrated. Such welded high-conductance CNT networks of functionalized CNTs could be useful for device and sensor applications, and may serve as high mechanical toughness mat fillers that are amenable to integration with nanocomposite matrices.
摘要翻译： 开发并展示了通过与空气暴露结合使用高电流密度来切割，变薄，焊接和化学官能化具有羧基和烯丙基部分的多壁碳纳米管（CNT）以及改变CNT膜的电性能的方法。 功能化CNT的这种焊接高电导CNT网络可用于器件和传感器应用，并且可以用作适于与纳米复合材料基体结合的高机械韧性垫填料。
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5.发明申请THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE 有权三维NAND器件和NAND器件中充电陷阱层分离和浮动栅格形成的方法公开(公告)号：US20140138760A1
公开(公告)日：2014-05-22
申请号：US14166162
申请日：2014-01-28
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/7682 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
摘要翻译： 单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。 该串还包括阻挡介电层，电荷存储区和隧道电介质。 第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。
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公开(公告)号：US20110014779A1
公开(公告)日：2011-01-20
申请号：US12458543
申请日：2009-07-15
申请人： Raghuveer S. Makala , Vance Dunton , Yoichiro Tanaka , Steven Maxwell , Tong Zhang , Steven J. Radigan
发明人： Raghuveer S. Makala , Vance Dunton , Yoichiro Tanaka , Steven Maxwell , Tong Zhang , Steven J. Radigan
IPC分类号： H01L21/20
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
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公开(公告)号：US20110014771A1
公开(公告)日：2011-01-20
申请号：US12656306
申请日：2010-01-25
申请人： Vance Dunton , Raghuveer S. Makala , Michael Chan
发明人： Vance Dunton , Raghuveer S. Makala , Michael Chan
IPC分类号： H01L21/822 , H01L21/306 , H01L21/302 , H01L21/20
CPC分类号： H01L27/101 , H01L21/32134 , H01L27/1021 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.
摘要翻译： 制造半导体器件的方法包括提供包含多个开口的绝缘层，在多个开口中形成第一导电类型半导体层，在多个开口中的第一导电类型半导体层上形成第二导电类型半导体层 并且使用第一导电类型半导体层的上表面作为停止来选择性地蚀刻第二导电类型半导体层，以在多个开口中形成凹部。
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8.发明授权公开(公告)号：US08772749B2
公开(公告)日：2014-07-08
申请号：US13047020
申请日：2011-03-14
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1675
摘要： In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种金属绝缘体金属（MIM）堆叠，其包括：（1）包含硅 - 锗（SiGe）合金的第一导电层; （2）电阻率切换层，包括形成在所述第一导电层上方的金属氧化物层; 和（3）形成在电阻率切换层上方的第二导电层。 存储单元可以由MIM堆叠形成。 提供了许多其他方面。
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公开(公告)号：US08520424B2
公开(公告)日：2013-08-27
申请号：US13157204
申请日：2011-06-09
申请人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S. Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
发明人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S. Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。
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10.发明申请Three Dimensional Horizontal Diode Non-Volatile Memory Array and Method of Making Thereof 有权三维水平二极管非易失性存储器阵列及其制作方法公开(公告)号：US20120091413A1
公开(公告)日：2012-04-19
申请号：US12905445
申请日：2010-10-15
申请人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Raghuveer S. Makala
发明人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Raghuveer S. Makala
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/249
摘要： A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
摘要翻译： 非易失性存储器件包含位于绝缘材料沟槽中的水平二极管的三维堆叠，多个存储元件，基本垂直延伸的多条字线和多个位线。 多个位线中的每一个具有沿着沟槽的至少一侧向上延伸的第一部分和基本水平延伸穿过水平二极管的三维叠层的第二部分。 每个水平二极管是非易失性存储器件的相应非易失性存储单元的转向元件，并且多个存储元件中的每一个位于相应的转向元件附近。
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